Patents by Inventor Ankit Parikh

Ankit Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11020375
    Abstract: Disclosed is an Edaravone dosage form and a use thereof in preparing a drug used for treating diseases related to oxidative stress, the dosage form being selected from a lipid-based delivery system, a solid dispersion, micelles and a co-solvent based formulation.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 1, 2021
    Assignee: SUZHOU AUZONE BIOLOGICAL TECHNOLOGY CO., LTD.
    Inventors: Xinfu Zhou, Ankit Parikh, Sanjay Garg
  • Publication number: 20190083463
    Abstract: Disclosed is an Edaravone dosage form and a use thereof in preparing a drug used for treating diseases related to oxidative stress, the dosage form being selected from a lipid-based delivery system, a solid dispersion, micelles and a co-solvent based formulation.
    Type: Application
    Filed: April 21, 2017
    Publication date: March 21, 2019
    Applicant: SUZHOU AUZONE BIOLOGICAL TECHNOLOGY CO., LTD.
    Inventors: Xinfu ZHOU, Ankit PARIKH, Sanjay GARG
  • Patent number: 7415549
    Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Kiran Vemula, Victor Lau, Pak-lung Seto, Nai-Chih Chang, William Halleck, Suresh Chemudupati, Ankit Parikh, Gary Y. Tsao
  • Publication number: 20070011333
    Abstract: Disclosed is an initiator port that implements a transport layer retry (TLR) mechanism. The initiator port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 11, 2007
    Inventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, Kiran Vemula, William Halleck, Ankit Parikh
  • Publication number: 20070002827
    Abstract: Disclosed is a target port that implements a transport layer retry (TLR) mechanism. The target port includes a circuit having a transmit transport layer and receive transport layer in which both the transmit and receive transport layers are coupled to a link. A transmit protocol processor of the transmit transport layer controls a TLR mechanism in a serialized protocol. A receive protocol processor of the receive transport layer is coupled to the transmit transport layer and likewise controls the TLR mechanism in the serialized protocol.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, Kiran Vemula, William Halleck, Ankit Parikh