Patents by Inventor Ankur Bal
Ankur Bal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8738679Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.Type: GrantFiled: September 23, 2009Date of Patent: May 27, 2014Assignee: STMicroelectronics International N.V.Inventors: Rakhel Kumar Parida, Ankur Bal, Anupam Jain
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Patent number: 8731214Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: GrantFiled: April 23, 2010Date of Patent: May 20, 2014Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Anupam Jain, Rakhel Kumar Parida
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Publication number: 20140132434Abstract: In an embodiment, a set of input samples are filtered to provide a set of filtered samples using an N-tap filter. A steady-state-response-output sample of the N-tap filter is determined from a N/2th sample of the set of filtered samples.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Ankur BAL, Neha BHARGAVA, Anupam JAIN
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Patent number: 8645445Abstract: The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.Type: GrantFiled: November 6, 2009Date of Patent: February 4, 2014Assignee: ST-Ericsson SAInventors: Ankur Bal, Anupam Jain
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Publication number: 20130110898Abstract: A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.Type: ApplicationFiled: May 10, 2012Publication date: May 2, 2013Applicant: STMicroelectronics International NVInventors: Ankur BAL, Anupam JAIN, Neha BHARGAVA
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Publication number: 20120176264Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.Type: ApplicationFiled: March 16, 2012Publication date: July 12, 2012Applicant: STMicroelectronics PVT LTD (INDIA)Inventors: Rakhel Kumar PARIDA, Ankur BAL, Anil KUMAR, Anupam JAIN
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Publication number: 20120166856Abstract: Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.Type: ApplicationFiled: June 29, 2011Publication date: June 28, 2012Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Ankur BAL, Anupam JAIN
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Patent number: 8159381Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.Type: GrantFiled: July 23, 2010Date of Patent: April 17, 2012Assignee: STMicroelectronics Pvt. Ltd.Inventors: Rakhel Kumar Parida, Ankur Bal, Anil Kumar, Anupam Jain
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Publication number: 20110279292Abstract: A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b?1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.Type: ApplicationFiled: July 23, 2010Publication date: November 17, 2011Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Rakhel Kumar Parida, Ankur Bal, Anil Kumar, Anupam Jain
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Publication number: 20110142254Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.Type: ApplicationFiled: April 23, 2010Publication date: June 16, 2011Applicant: STMICROELECTRONICS PVT., LTD.Inventors: Ankur BAL, Anupam Jain, Rakhel Kumar Parida
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Publication number: 20110004647Abstract: An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins.Type: ApplicationFiled: September 23, 2009Publication date: January 6, 2011Applicant: STMicroelectronics Pvt. Ltd.Inventors: Rakhel Kumar PARIDA, Ankur BAL, Anupam Jain
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Patent number: 7856467Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.Type: GrantFiled: December 29, 2005Date of Patent: December 21, 2010Assignee: STMicroelectronics PVT. Ltd.Inventors: Parvesh Swami, Ankur Bal
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Publication number: 20100121897Abstract: The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption.Type: ApplicationFiled: November 6, 2009Publication date: May 13, 2010Applicant: ST Wireless SAInventors: Ankur Bal, Anupam Jain
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Patent number: 7180792Abstract: An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device includes a group of one or more data latches, each including a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring significant additional circuitry.Type: GrantFiled: February 28, 2003Date of Patent: February 20, 2007Assignee: STMicroelectronics Pvt. Ltd.Inventors: Ankur Bal, Manish Agarwal
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Publication number: 20060195503Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.Type: ApplicationFiled: December 28, 2005Publication date: August 31, 2006Applicant: STMICROELECRONICS PVT. LTD.Inventors: Parvesh Swami, Ankur Bal
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Patent number: 7038489Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.Type: GrantFiled: June 14, 2002Date of Patent: May 2, 2006Assignee: STMicroelectronics Ltd.Inventor: Ankur Bal
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Patent number: 7030648Abstract: This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.Type: GrantFiled: December 18, 2003Date of Patent: April 18, 2006Assignee: STMicroelectronics PVT, Ltd.Inventors: Ankur Bal, Namerita Khanna
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Patent number: 6888374Abstract: An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.Type: GrantFiled: June 17, 2003Date of Patent: May 3, 2005Assignee: STMicroelectronics Pvt. Ltd.Inventor: Ankur Bal
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Publication number: 20040178821Abstract: This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.Type: ApplicationFiled: December 18, 2003Publication date: September 16, 2004Applicant: STMICROELECTRONICS PVT. LTD.Inventors: Ankur Bal, Namerita Khanna
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Patent number: RE41561Abstract: A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.Type: GrantFiled: April 25, 2008Date of Patent: August 24, 2010Inventor: Ankur Bal