Abstract: A phase comparator and data separator is disclosed capable of establishing a detection window of the order of 100 percent of the clock cycle at a data recovery rate at least as great as 100 MHz. One of the preferred embodiments of the invention comprises three bistable flip-flops interconnected with OR gates to respond to a data input pulse stream and a clock pulse stream to provide, in response to each data pulse, a reference pulse having a width equal to the bit cell period and a variable pulse having a duration which is greater or less than the reference pulse duration in accordance with the direction and amount of time displacement of the input pulse from the center of the bit cell in which the input pulse occurs.