Abstract: Systems and methods are provided for dynamically modeling and depicting overall emissions of the aviation industry and changes thereto when taking into account, for example, traffic growth and introduction of sustainability strategies, such as new and/or improved technologies, an increase in operational efficiency, and carbon offsets. Using the dynamic tool described herein, users can define scenarios on how to reduce emissions through the introduction of different sustainability strategies, both statically and over time, analyze the impact of those strategies on emissions, and understand the dependencies between select strategies.

Abstract: A fuel injector for a gas turbine engine combustor is provided that includes a swirler, a mounting stage, and a distributor. The swirler has a shaft, a collar, a throat section, and first and second axial ends. The throat section includes an inner radial surface that defines a central passage that extends between the swirler inner bore and the collar. The collar includes a plurality of apertures extending therethrough disposed radially outside of the central passage. The mounting stage is disposed in the inner bore, and has an annular flange, a central hub, and at least one strut. The distributor has a stem attached to a head. The stem has a distal end opposite the head portion engaged with the central hub. The head portion has an end surface and a side surface. The distributor is selectively positionable relative to the throat section.

Abstract: The present invention relates to a process for producing a food article consisting of an edible composition having an elongated member extending therefrom, the edible composition having a water content of less than 5 wt. %. The present invention also relates an edible composition and to the of the edible composition for preparing a meal or snack.

Abstract: A system and computer-implemented method of altering perceptibility of depth in an image. The method comprises receiving a desired change in the perceptibility of depth in the image; receiving a depth-map corresponding to the image; and determining at least one characteristic of the image. The method further comprises applying an image process to the image, the image process varying in strength according to the depth map, and in accordance with a non-linear predetermined mapping relating a strength of the applied image process to a change in the perceptibility of depth, the mapping being determined with respect to the identified characteristic.

Abstract: A system and computer-implemented method of altering perceptibility of depth in an image. The method comprises receiving a desired change in the perceptibility of depth in the image; receiving a depth-map corresponding to the image; and determining at least one characteristic of the image. The method further comprises applying an image process to the image, the image process varying in strength according to the depth map, and in accordance with a non-linear predetermined mapping relating a strength of the applied image process to a change in the perceptibility of depth, the mapping being determined with respect to the identified characteristic.

Abstract: A plastic particle detector for detecting biological and other fluorescent materials is disclosed. The detector detects the fluorescence and scattering signals from these materials using deep UV excitation. The detector is fabricated using plastic materials and exploits the properties of lower manufacturing costs, lower materials costs, light weight, ruggedness and assembly ease offered by plastics, while eliminating stray fluorescence signals ordinarily generated by plastic materials.

Abstract: A method of projecting a user interface for a plurality of users with a calculated orientation is provided. The method detects gestures from the plurality of users associated with a projection of the user interface and applies a weighting, representing a level of interaction between a user and the user interface, to each of the detected gestures according to a gesture type and a context of the user interface when the gesture was detected, the context including consideration of positions of the plurality of users. An orientation of the user interface is calculated based on the weighting of the detected gestures and the context of the user interface, and the user interface is projected for the plurality of users with the calculated orientation.

Abstract: This invention relates to a color indicator for pipette tips that aids in the removal of the supernatant from extraction tubes where it is difficult to differentiate the tip of clear or translucent pipette from the clear opaque tube containing supernatant and the pellet. The colorized tip may also be sold as an assembly with color-coded extraction tubes for identification purposes.

Abstract: A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comparing the ALU output with the inverted pattern to produce a second output; bitwise masking the first and second outputs using a mask of a plurality of masks to produce third and fourth output bits; combining the third and fourth output bits to produce first and a second output comparison bits; and storing the first and second output comparison bits in a memory.

Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Abstract: An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.

Abstract: A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.

Abstract: An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Abstract: A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Abstract: A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode.