Abstract: Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.

Abstract: Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

Abstract: Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell sub-circuits, which include ? Josephson junctions, connected together by the interconnects. Each of the unit cell sub-circuits can be configured as a looped or linear arrangement. The unit cell sub-circuits and interconnects provide a fast, dense memory technology for reciprocal quantum logic (RQL), suitable for low-level caches and other memories collocated with an RQL processor.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell sub-circuits, which include ? Josephson junctions, connected together by the interconnects. Each of the unit cell sub-circuits can be configured as a looped or linear arrangement. The unit cell sub-circuits and interconnects provide a fast, dense memory technology for reciprocal quantum logic (RQL), suitable for low-level caches and other memories collocated with an RQL processor.

Abstract: A Josephson memory array and logic circuits use quasi-long-Josephson-junction interconnects to propagate signals at fast speeds and low energy expense, while permitting for memory arrays as dense fabrics of relatively simple unit cell sub-circuits, which include it Josephson junctions, connected together by the interconnects. Each of the unit cell sub-circuits can be configured as a looped or linear arrangement. The unit cell sub-circuits and interconnects provide a fast, dense memory technology for reciprocal quantum logic (RQL), suitable for low-level caches and other memories collocated with an RQL processor.

Abstract: Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: Capacitively coupled superconducting integrated circuits powered using alternating current clock signals are described. An example superconducting integrated circuit includes a first clock line coupled via a first capacitor to a first superconducting circuit including a first Josephson junction, where the first capacitor is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit. The superconducting integrated circuit further includes a second clock line coupled via a second capacitor to a second superconducting circuit including a second Josephson junction, where the second capacitor is configured to receive a second clock signal having a second phase and couple a second bias current to the second superconducting circuit, and where the second phase is different from the first phase.

Abstract: One example includes a superconducting transmission line driver system. The system includes an input stage configured to receive an input pulse and an AC bias current source configured to provide an AC bias current. The system also includes an amplifier coupled to the input stage and configured to generate a plurality of sequential SFQ pulses based on the input pulse in response to the AC bias current. The system further includes a low-pass filter configured to filter the plurality of sequential SFQ pulses to generate an amplified output pulse that is output to a transmission line.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: One embodiment includes a clock distribution system. The system includes a standing-wave resonator configured to receive and to resonate a sinusoidal clock signal. The standing-wave resonator includes at least one anti-node portion associated with a peak current amplitude of the sinusoidal clock signal. The system also includes at least one clock line interconnecting each of the at least one anti-node portion and an associated circuit. The at least one clock line can be configured to propagate the sinusoidal clock signal for timing functions associated with the associated circuit.

Abstract: Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set of pulses, and a second input terminal for receiving a second set of pulses is provided. The first section may be configured to pass a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but to not pass two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal. The second section, coupled to the first section, may be configured to, in response to the single pulse, generate a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.

Abstract: One embodiment describes a Josephson current source system comprising a flux-shuttle loop that is inductively coupled with an AC input signal. The flux-shuttle loop includes a plurality of stages each comprising at least one Josephson junction. The plurality of stages can be spaced about the flux shuttle loop. Each of a plurality of pairs of the plurality of stages are configured to concurrently trigger in a sequence via the respective at least one Josephson junction in response to the AC input signal and to provide a respective pair of single-flux quantum (SFQ) pulses that move sequentially and continuously through each stage of the plurality of stages around the flux-shuttle loop via each of the at least one Josephson junction of each of the respective stages that results in a DC output current being provided through an output inductor.

Abstract: Superconducting circuits based devices and methods, including reciprocal quantum logic (RQL) based devices and methods are provided. In one example, a device comprising an output terminal, a first input terminal for receiving a first set of pulses, and a second input terminal for receiving a second set of pulses is provided. The first section may be configured to pass a single pulse received during a single clock cycle at any of the first input terminal or the second input terminal, but to not pass two or more positive pulses received during a single clock cycle at the first input terminal and the second input terminal. The second section, coupled to the first section, may be configured to, in response to the single pulse, generate a negative pulse after a predetermined fraction of a single clock cycle after providing a positive pulse at the output terminal.

Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.