Abstract: A method and system are provided. The method includes condensing, by a processor, an original voxel-beamlet matrix stored in a memory device into a reduced dataset for proton beam simulation and therapy. The original voxel-beamlet matrix has a row for each of a plurality of voxels in a three-dimensional patient volume and a column for each of a plurality of radiation beamlets. The condensing step includes determining protobeams to be extracted from the original voxel-beamlet matrix. The protobeams are columns (i) selected from the original voxel-beamlet matrix based on comparisons performed between the columns in the original voxel-beamlet matrix or (ii) created by combining at least some of the columns in the original voxel-beamlet matrix, in a matrix condensing process. The condensing step further includes extracting the protobeams from the original voxel-beamlet matrix. The condensing step also includes storing the protobeams as the reduced dataset in the memory device.

Abstract: A method and system are provided. The method includes condensing, by a processor, an original voxel-beamlet matrix stored in a memory device into a reduced dataset for proton beam simulation and therapy. The original voxel-beamlet matrix has a row for each of a plurality of voxels in a three-dimensional patient volume and a column for each of a plurality of radiation beamlets. The condensing step includes determining protobeams to be extracted from the original voxel-beamlet matrix. The protobeams are columns (i) selected from the original voxel-beamlet matrix based on comparisons performed between the columns in the original voxel-beamlet matrix or (ii) created by combining at least some of the columns in the original voxel-beamlet matrix, in a matrix condensing process. The condensing step further includes extracting the protobeams from the original voxel-beamlet matrix. The condensing step also includes storing the protobeams as the reduced dataset in the memory device.

Abstract: A method and system are provided. The method includes splitting, by a processor based on radiation beamlet contributions to neighboring voxels, at least one row in a voxel-beamlet matrix and corresponding elements of a target dose vector prior to, and in preparation for, a regression operation. The voxel-beamlet matrix has a row for each of a plurality of voxels in a three-dimensional patient volume and a column for each of a plurality of radiation beamlets. The target dose vector represents a desired energy amount for each of the plurality of voxels in the three-dimensional patient volume. The target dose vector corresponds voxel-by-voxel to rows in the voxel-beamlet matrix. The method further includes performing, by the processor, the regression operation on the voxel-beamlet matrix and target dose vector to obtain beamlet weights. The method also includes determining an actual radiation dosing scheme for a given patient based on the beamlet weights.

Abstract: An approach is provided that improves a question answering (QA) computer system by reducing a number of vague questions submitted to the QA system. When a question is submitted to the QA system, the approach performs a vagueness question analysis on the question. The vagueness question analysis results in a vagueness score. The question is submitted to the QA system in response to the vagueness score reaching a threshold value that indicates a lack of vagueness in the question. The approach inhibits submission of the question to the QA system in response to the vagueness score failing to reach the threshold value.

Abstract: An approach is provided that improves a question answering (QA) computer system by reducing a number of vague questions submitted to the QA system. When a question is submitted to the QA system, the approach performs a vagueness question analysis on the question. The vagueness question analysis results in a vagueness score. The question is submitted to the QA system in response to the vagueness score reaching a threshold value that indicates a lack of vagueness in the question. The approach inhibits submission of the question to the QA system in response to the vagueness score failing to reach the threshold value.

Abstract: A system and a computer program product are provided for evaluating question-answer pairs in an answer key by comparing a first answer key answer to a plurality of candidate answers to determine if the answer key may have a problem if the plurality of candidate answers are more similar to one another than to the first answer and to determine if the plurality of candidate answers has gradient information which may be used to update the answer key if not already included in the answer key.

Abstract: A computer-implemented method for creating question-answer pairs is provided. The computer-implemented method includes leveraging domain specific resources including, at least one or more of lexicons, glossaries, or knowledge bases for constructing templates for creating the question-answer pairs. The computer implemented method further includes leveraging user experiences of a plurality of users for constructing templates. The computer implemented method further includes eliminating erroneous question-answer pairs based on templates specifications of a heuristic process of the constructed templates.

Abstract: Simulating particle beam interactions includes identifying a set of n functions F1, F2, . . . , Fn corresponding to a plurality of different physical aspects of a particle beam, performing simulations of each Fi using a full physics model, selecting for each Fi a distribution function fi that models relevant behavior and reducing computation of the full physics model for each Fi by replacing Fi with a distribution function fi. The computation reduction includes comparing a set of simulations wherein each fi replaces its respective Fi to determine if relevant behavior is accurately modeled and selecting one of fi or Fi for each n, for a Monte Carlo simulation based on a runtime and accuracy criteria.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test.

Abstract: A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island source voltage (VDDI1, VDDI2), and a testing circuit (116), coupled to the voltage islands, and powered by a global source voltage (Vg) that is always on during test, wherein each island source voltage may be independently controlled (106, 108) during test.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

Abstract: A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.