Patents by Inventor Anne Vandooren
Anne Vandooren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230197522Abstract: The disclosure relates to a method for forming a semiconductor device. The method includes forming a device layer stack on a substrate, the device layer stack having a first sub-stack comprising a first sacrificial layer and on the first sacrificial layer a channel layer defining a topmost layer of the first sub-stack, and a second sub-stack on the first sub-stack and including a first sacrificial layer defining a bottom layer of the second sub-stack, and a second sacrificial layer on the first sacrificial layer, wherein said first sacrificial layers are formed of a first sacrificial semiconductor material, the second sacrificial layer is formed of a second sacrificial semiconductor material, and the channel layer is formed of a semiconductor channel material, and wherein a thickness of the second sub-stack exceeds a thickness of the first sacrificial layer of the first sub-stack.Type: ApplicationFiled: December 13, 2022Publication date: June 22, 2023Inventors: Boon Teik Chan, Anne Vandooren, Julien Ryckaert, Naoto Horiguchi
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Publication number: 20230197830Abstract: A method for forming a stacked field-effect transistor device is provided.Type: ApplicationFiled: December 13, 2022Publication date: June 22, 2023Inventors: Boon Teik Chan, Anne Vandooren, Naoto Horiguchi
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Publication number: 20230197726Abstract: Example embodiments relate to methods for forming a stacked FET device. An example method includes forming a bottom FET device that includes a source, a drain, at least one channel layer between the source and drain, and a bottom gate electrode arranged along the at least one channel layer. The method also includes forming a bonding layer over the bottom FET. Additionally, the method includes forming a top FET device on the bonding layer. Forming the top FET device includes forming a device layer structure. The device layer structure includes at least one channel layer of a channel semiconductor material and a top sacrificial layer of a sacrificial semiconductor material. Further, the method includes replacing the top sacrificial layer with a dummy layer of a dielectric dummy material, forming a gate-to-gate contact trench, depositing gate electrode material, and forming a source and a drain of the top FET device.Type: ApplicationFiled: December 12, 2022Publication date: June 22, 2023Inventors: Book Teik Chan, Dunja Radisic, Anne Vandooren, Juergen Boemmels
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Publication number: 20190273115Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.Type: ApplicationFiled: May 22, 2019Publication date: September 5, 2019Applicant: IMEC VZWInventors: Amey Mahadev Walke, Anne Vandooren, Nadine Collaert
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Patent number: 10367031Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.Type: GrantFiled: September 12, 2017Date of Patent: July 30, 2019Assignee: IMEC VZWInventors: Amey Mahadev Walke, Anne Vandooren, Nadine Collaert
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Publication number: 20180076260Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.Type: ApplicationFiled: September 12, 2017Publication date: March 15, 2018Applicant: IMEC VZWInventors: Amey Mahadev Walke, Anne Vandooren, Nadine Collaert
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Patent number: 9419114Abstract: A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.Type: GrantFiled: January 16, 2015Date of Patent: August 16, 2016Assignees: IMEC VZW, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Amey Mahadev Walke, Anne VanDooren, Krishna Kumar Bhuwalka
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Publication number: 20150206958Abstract: A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.Type: ApplicationFiled: January 16, 2015Publication date: July 23, 2015Inventors: Amey Mahadev Walke, Anne VanDooren, Krishna Kumar Bhuwalka
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Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device
Patent number: 8415209Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.Type: GrantFiled: April 8, 2011Date of Patent: April 9, 2013Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Rita Rooyackers, Daniele Leonelli, Anne Vandooren, Anne S. Verhulst, Roger Loo, Stefan De Gendt -
Publication number: 20110253981Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.Type: ApplicationFiled: April 8, 2011Publication date: October 20, 2011Applicants: Katholieke Universiteit Leuven, K.U. LEUVEN R&D, IMECInventors: Rita Rooyackers, Daniele Leonelli, Anne Vandooren, Anne S. Verhulst, Roger Loo, Stefan De Gendt
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Publication number: 20050101069Abstract: A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric is formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer and the polysilicon with the patterned photoresist in place wherein the etching produces a polysilicon width that is less than a width of the capping layer to create voids under the capping layer adjacent sidewalls of the polysilicon where the confined spacers can be formed.Type: ApplicationFiled: October 28, 2003Publication date: May 12, 2005Inventors: Leo Mathew, Rode Mora, Bich-Yen Nguyen, Tab Stephens, Anne Vandooren
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Patent number: 6753216Abstract: A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).Type: GrantFiled: October 31, 2002Date of Patent: June 22, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Bich-Yen Nguyen, Daniel Thanh-Khac Pham, Anne Vandooren
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Publication number: 20040084674Abstract: A semiconductor fabrication process and structure in which a dielectric structure (106) is formed upon a substrate (102). Silicon is then deposited and processed to form a crystalline silicon wall (118) that envelopes the dielectric structure (106) and is physically and electrically isolated from the substrate (102). A gate dielectric film (130) is formed over at least two surfaces of the silicon wall (118) and a gate electrode film (132) is formed over the gate dielectric (130). The gate electrode film (132) is then patterned followed by conventional source/drain implant processing. Portions of the silicon wall (118) disposed on either side of the gate electrode (140) may then be contacted to form source/drain structures (150). In this manner, the portion of the silicon wall (118) covered by the gate electrode (140) comprises a transistor channel region having multiple surfaces controlled by gate electrode (140).Type: ApplicationFiled: October 31, 2002Publication date: May 6, 2004Inventors: Leo Mathew, Bich-Yen Nguyen, Daniel Thanh-Khac Pham, Anne Vandooren
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Patent number: 6689676Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.Type: GrantFiled: July 26, 2002Date of Patent: February 10, 2004Assignee: Motorola, Inc.Inventors: Daniel Thanh-Khac Pham, Al T. Koh, Yeong-Jyh T. Lii, Robert F. Steimle, Anne Vandooren, Ricardo Garcia, Kimberly G. Reid, Marc Rossow, James P. Geren
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Publication number: 20040018681Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Inventors: Daniel Thanh-Khac Pham, Bich-Yen Nguyen, James K. Schaeffer, Melissa O. Zavala, Sherry G. Straub, Al T. Koh, Yeong-Jyh T. Lii, Robert F. Steimle, Anne Vandooren, Ricardo Garcia, Kimberly G. Reid, Marc Rossow, James P. Geren