Patents by Inventor Annekathrin Zeun

Annekathrin Zeun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8674416
    Abstract: Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz
  • Patent number: 8609482
    Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Martin Trentzsch
  • Patent number: 8324119
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz
  • Publication number: 20120282760
    Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
    Type: Application
    Filed: July 13, 2012
    Publication date: November 8, 2012
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Martin Trentzsch
  • Patent number: 8293596
    Abstract: A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced high-k metal gate stack may be formed with superior uniformity.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 23, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Thorsten Kammler
  • Patent number: 8247282
    Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: August 21, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Martin Trentzsch
  • Publication number: 20110129970
    Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.
    Type: Application
    Filed: October 15, 2010
    Publication date: June 2, 2011
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Martin Trentzsch
  • Publication number: 20110027952
    Abstract: A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced high-k metal gate stack may be formed with superior uniformity.
    Type: Application
    Filed: July 23, 2010
    Publication date: February 3, 2011
    Inventors: Stephan Kronholz, Carsten Reichel, Annekathrin Zeun, Thorsten Kammler
  • Publication number: 20100289094
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 18, 2010
    Inventors: Carsten Reichel, Thorsten Kammler, Annekathrin Zeun, Stephan Kronholz