Abstract: A control circuit generates an output based on the first signal and the second signal by encoding the output to be a multi-state signal having at least three states. A magnitude of the multi-state signal generated by the controller varies depending on binary states of the first signal and the second signal. The controller utilizes the output (i.e., the multi-state signal) to control a switching circuit. A driver circuit receives the output generated by the control circuit. In one embodiment, the multi-state signal has more than two different logic states. The driver decodes the multi-state signal for generating signals to control switches in the switching circuit. One signal generated by the driver circuit is a pulse width modulation signal; another signal generated by the driver circuit is an enable/disable signal.

Abstract: An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

Abstract: An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

Abstract: A circuit for correcting baseline wander in a transmitter which includes a main signal current driver driving a first winding of a two-winding transformer which first winding is in parallel with a termination impedance matching load, in which a compensation current driver is coupled in parallel with the main signal current driver for adding its current to current of the main signal current driver. A correction signal control input is provided to the compensation driver. A sample-and-hold circuit is connected across the first winding, an error amplifier having a first pair of inputs is connected across the first winding and a second pair of inputs are connected to the output of the sample and hold circuit. These provide an error signal resulting from a difference of signals appearing at its respective pairs of inputs.

Abstract: An equalizer comprising a pair of high pass filters for receiving an input signal, each filter having gain, a first of the filters having gain which is substantially flat within its passband, a second of the filters having gain over a range of its passband which is controlled by an error signal, a differential amplifier for generating the error signal, having an output applied to a control input of the second filter, a pair of broadband amplitude peak detectors each for receiving an output signal of a respective one of the filters, apparatus for applying loop signals derived from outputs of the filters and passing though the peak detectors to corresponding inputs of the differential amplifier, apparatus for providing an offset to a loop signal derived from the output of the first filter, and apparatus for providing an output signal from the output of the second filter.

Abstract: A translation circuit for mixed logic voltage signals is comprised of a first pair of self-biasing common-mode level shifters for receiving positive and negative polarity input signals respectively of a balanced input signal, each level shifter having a control input for receiving a ratio control signal, and having first level shifter nodes for providing the same polarity output signals, a second pair of self-biasing common-mode level shifters, each connected in parallel with a corresponding variable ratio level shifter, the second pair of level shifters having fixed level shift ratios, a circuit connected to level shifter nodes of the second pair of level shifters for providing and storing a signal which is a sum of voltages appearing at the level shifter nodes, and a circuit for applying the stored signal to the control inputs.

Abstract: Low-cost apparatus and method for achieving a moderately-precise resistance value into an integrated circuit without the use of resistive trimming or complex feedback loops. The invention has direct application to the production of integrated BiCMOS circuits making use of Delay Lines and/or Voltage-Controlled Ring Oscillators where a .+-.10% tolerance in delay time or frequency is acceptable. When incorporated into a PLL, it also presents advantages where tighter tolerances are required, because of its low inherent jitter. By the use of a single off-chip component, this invention overcomes variations in the operating circuit otherwise arising from chip fabrication irregularities, power supply voltage fluctuations, and ambient temperature drift. In the Preferred Embodiment of the present invention, the resistive element is used as the load resistor of a high-frequency ECL delay cell; the element is a controlled MOSFET resistor in parallel with a fixed diffusion resistor.