Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method may comprise encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is formed to reduce full-swing transitions between successive digital signal transmissions.

Abstract: A signaling system having an equalizing transmitter and equalizing receiver. The equalizing transmitter transmits a signal to a receive circuit. A first sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a first threshold, and a second sampling circuit within the equalizing receiver samples the signal to determine whether the signal exceeds a second threshold. A drive strength of the equalizing transmitter and a drive strength of an equalizing signal driver within the equalizer are adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds.

Abstract: A signaling system having first and second sampling circuits and an output driver circuit. The first sampling circuit samples a first signal generated by the output driver circuit to determine whether the first signal exceeds a first threshold. The second sampling circuit samples the first signal to determine whether the first signal exceeds a second threshold. The drive strength of the output driver circuit is adjusted based, at least in part, on whether the first signal exceeds the first and second thresholds, and the second threshold is adjusted based, at least in part, on whether the first signal exceeds the second threshold.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method may comprise encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is formed to reduce full-swing transitions between successive digital signal transmissions.

Abstract: A receiver employs non-linear threshold compensation to adjust input sample values from a single mode fiber to mitigate effects of polarization mode dispersion. A difference S between values for i) a decision for the current input sample and ii) a decision for the previous input sample is generated that indicates whether a transition between logic values occurred in the input data and the direction of transition (sign/phase). Two values are generated to determine a magnitude c of correction combined with the sign/phase (difference S) to generate a correction value. An error value e is generated as the magnitude of the difference between i) the decision for the input sample and ii) the input sample. A value d is calculated as the magnitude of the difference between i) the current input sample and ii) the previous input sample is also generated. The value d represents a relative “closeness” in value between two consecutive input samples.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a code in a multi-level signaling system, wherein the code has a characteristic wherein a signal transition is periodically unused. Such a method may comprise modifying the code such that the periodically unused signal transition is used to represent additional information.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic such that at least one signal level is periodically unused. The method comprises utilizing the at least one periodically unused signal level in a codeword that has been encoded using the transition-limiting code so as to represent additional information in the multi-level signaling system.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A technique for determining an optimal transition-limiting code for use in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for determining an optimal transition-limiting code for use in a multi-level signaling system. Such a method comprises determining a coding gain for each of a plurality of transition-limiting codes, and selecting one of the plurality of transition-limiting codes having a largest coding gain for use in the multi-level signaling system.

Abstract: A technique for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for utilizing spare bandwidth resulting from the use of a transition-limiting code in a multi-level signaling system, wherein the transition-limiting code has a characteristic wherein a signal level is periodically unused. Such a method may comprise modifying the transition-limiting code such that the periodically unused signal level is used to represent additional information.

Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method comprises encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting the sets of P symbols.

Abstract: A sequence of information bits are parity-check coded in a parity generator utilizing an m+1-bit parity-check code. The m+1-bit parity-check code may be formed as a combination of an otherwise conventional m-bit parity-check code and an overall parity bit. The overall parity bit provides an indication of the parity of a plurality of composite or single error events associated with decoding of the parity codewords. The parity generator includes a single-parity encoder for generating the overall parity bit, and a parity generator matrix element for generating a codeword based on the m-bit parity-check code, with a given one of the codewords of the m+1-bit parity-check code formed as a combination of the codeword based on the m-bit parity-check code and the overall parity bit.

Abstract: An output signal of a single mode fiber (SMF) is spectrally shaped to achieve characteristics of a predefined channel “target” response. The target response is that of a partial-response, maximum-likelihood channel with additive white Gaussian noise. A receiver employs a maximum-likelihood sequence estimation (MLSE) detector having its detection algorithm, such as a Viterbi algorithm (VA), matched to the target response. Thus, state, branch, and path metric calculations for a Viterbi trellis may be optimized for a channel having this target response.

Abstract: A receiver employs non-linear threshold compensation to adjust input sample values from a single mode fiber to mitigate effects of polarization mode dispersion. A difference S between values for i) a decision for the current input sample and ii) a decision for the previous input sample is generated that indicates whether a transition between logic values occurred in the input data and the direction of transition (sign/phase). Two values are generated to determine a magnitude c of correction combined with the sign/phase (difference S) to generate a correction value. An error value e is generated as the magnitude of the difference between i) the decision for the input sample and ii) the input sample. A value d is calculated as the magnitude of the difference between i) the current input sample and ii) the previous input sample is also generated. The value d represents a relative “closeness” in value between two consecutive input samples.

Abstract: A sequence of information bits are parity-check coded in a parity generator utilizing an m+1-bit parity-check code. The m+1-bit parity-check code may be formed as a combination of an otherwise conventional m-bit parity-check code and an overall parity bit. The overall parity bit provides an indication of the parity of a plurality of composite or single error events associated with decoding of the parity codewords. The parity generator includes a single-parity encoder for generating the overall parity bit, and a parity generator matrix element for generating a codeword based on the m-bit parity-check code, with a given one of the codewords of the m+1-bit parity-check code formed as a combination of the codeword based on the m-bit parity-check code and the overall parity bit.

Abstract: Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.