Abstract: An output of a power-on-reset (POR) circuit is coupled to another circuit which needs to have the logic states thereof reset during each time a power supply used to power same is switched on. The POR circuit includes a first input circuit for generating an output signal that tracks the power supply output voltage Vdd approximately a first predetermined threshold below Vdd, as Vdd ramps up and further includes a second input circuit which generates an output signal which tracks approximately a second predetermined threshold above a second fixed voltage level, e.g., ground. The POR circuit further includes a comparator which compares the output signals from the first and second input circuits and switches an output signal thereof from a first to a second logic state once the input circuit output signals cross each other. A buffer is typically coupled to the output of the comparator to limit loading on same so as not to affect the comparator switching point.

Abstract: A driver circuit, which uses two serially connected enhancement mode n-channel MOS transistors in which the pullup transistor of the two transistors has no p-type implant in the channel region thereof and the pulldown transistor of the pair is a normlal enhancement mode transistor having a p-type threshold control implant in the channel thereof, is useful as a driver circuit for CMOS circiuts. The pullup transistor is designed to have a threshold of about 0 volts at zero back gate bias and the pulldown transistor is designed to have a threshold voltage of about 0.7 volts at zero back gate bias.