Abstract: A data pulse receiver includes a data regenerator and a peak detector, both having set-reset flip-flops (RS-FFs) to generate hysteresis which is varied based on its tail current provided to the RS-FF. The regenerator regenerates data from a differential signal derived from an incoming data signal. The peak detector monitors the peak level of the differential signal derived and its output adjust automatically the tail currents of the data regenerator and the peak detector. The receiver also includes impedance matching networks connected to the data regenerator and the peak detector. The input impedances for both networks are essentially the same. The tail currents for the two RS-FFs of the regenerator and the peak detector are essentially equal and it ensures precise cancellation of non-linear effects.

Abstract: A gyrator includes shunt or feedback nodal capacitors and shunt lossy inductors without shunt load resistors. The effective nodal capacitance is reduced by the introduction of the shunt lossy inductors. The inductors act to discriminate against injected power supply noise, resulting in improved oscillator phase noise. The inductors produce less dc voltage drop than the resistive load, so that larger linear oscillation is obtained with improved oscillator phase noise. The gyrator includes an automatic gain control circuit and a tuning control circuit which are separate from each other and fast and slow acting control loops which are augmented with each other.

Abstract: A microwave differential amplifier comprises a first and a second matched NMOS device, each connected with the source to a common bias node, the gate to an input port for receiving a differential input signal and with the drains to an output port for providing a differential output signal. The Miller capacitors of each device provide the necessary feedback between the input and output ports for shifting the phase of the differential output signal with respect to the phase of the differential input signal with 45.degree. at a predetermined frequency. The operating point of the NMOS devices is maintained in the linear region of the respective transfer characteristic, using matched loads and a corresponding bias current. The loads may be resistors, in which case AGC is used for maintaining a constant bias current, or active loads. A VCO built with four such differential amplifiers in a gyrator configuration oscillates at the predetermined frequency and has eight output signals.

Abstract: A low noise linear amplifier and a microwave voltage controlled oscillator constructed from such amplifier. Each amplifier within the VCO utilizes a ratioed transistor configuration to generate a linear output over a wide range of inputs. Output current from the amplifier is split into a main output current and components of in-phase and 180.degree. out-of-phase current. A logarithmic tuning control combines the components of in-phase and 180.degree. out-of-phase currents in inverse ratio to provide a constant d.c. feedback current.

Abstract: A linear bipolar junction transistor amplifier. The linear gain is achieved by an offset voltage created by ratioed transistors wherein the ratio is an integer. The ratios are achieved either by connecting equal transistors in parallel or by employing multiple emitters on a single transistor. This results in a linear amplifier which is substantially independent of manufacturing process tolerance variations as well as power supply and temperature variations.

Abstract: A low power (10 mW), high-speed (50 Mb/s) digital driver is formed from three analogue components: level shifter to limit the output swing, waveshaper to limit the slew-rate of the output transition, and a Class AB output stage to buffer the signal. The components afford flexibility to meet the demands of different applications. The driver can be limited to 1V swing for terminated applications such as for backplanes, or it can be limited to 1V swing for unterminated applications such as intraboard (PCB) communication.

Abstract: A gyrator based resonator comprises first and second differential amplifiers cross coupled to form a quadrature phase voltage controlled oscillator. The differential amplifier circuits include matched transistor pairs and associated transconductance adjusting components to control the resonant frequency of the resonator. Transconductance delay and admittance loss elements are also provided and these elements serve to control the loop gain of the resonator. A loop gain greater than unity results in the resonator oscillating while a loop gain less than unity produces a bandpass filter. A resonator having gain less than unity may be slaved to a similar resonator having gain adjusted to be greater than unity thus creating a low noise oscillator and tracking filter.

Abstract: A differential amplifier includes a bias current source and a current dividing circuit for controllably dividing a bias current between first and second current paths. A first pair of matched transistors is connected as a differential pair between matched load impedances and the first current path. A second pair of matched transistors is connected as a differential pair between the matched load impedances and the second current path. Differential inputs of the second differential pair are connected to corresponding differential inputs of the second differential pair. The transistors of the first and second pairs have different emitter areas. Matched capacitors may be connected between respective differential inputs and differential outputs of the differential amplifier. The load impedances may be tapped to provide outputs having a lower differential gain. The differential amplifier is useful for building resonant circuits, for example voltage controlled oscillators having high Q factors.

Abstract: A resonant circuit comprises first and second amplifiers. An input of the second amplifier is coupled to an output of the first amplifier, and an output of the second amplifier is cross-coupled to an input of the first amplifier. The first amplifier has a first gain and a 90 degree phase shift between its input and its output at a resonant frequency of the resonant circuit. The second amplifier has a second gain and a 90 degree phase shift between its input and its output at the resonant frequency of the resonant circuit. The second gain is different from the first gain. The resonant circuit can have a first port and second ports coupled to an input and an output respectively of one of the first and second amplifiers. Because the gains of the first and second amplifiers differ, the gain from the first port to the second port of the resonant circuit will differ from the gain from the second port to the first port.

Abstract: A BiCMOS logic circuit with Schottky-diode emulator is formed from three NMOS field-effect transistors, a PMOS field-effect transistor, a npn bipolar transistor and a load element. First and second NMOS transistors and the PMOS transistor are connected serially between ground and a positive supply voltage. The input signal to the circuit is connected to the gate of the first NMOS transistor and the gate of the PMOS transistor, each of which sits on an opposite side of the second NMOS transistor. The drain and gate of the second NMOS transistor are connected to each other and to the drain and gate of the third NMOS transistor. The drain of the first NMOS transistor is connected to the base of the npn transistor, which has its collector connected through a load to the supply voltage. The source of the third NMOS transistor is also connected to the collector of the npn transistor.

Abstract: A filter control circuit uses a compound FET as a resistance element. The compound FET includes parallel FETs having different gate widths to provide different drain-source resistance characteristics, which overlap to provide an extended operating region, that approaches a linear curve for the combined resistance characteristic. The control voltage used to control the compound FET may be coupled to like compound FETs in the filter being controlled.

Abstract: Telephone numbers are stored and retrieved for automatic redialling by an arrangement that includes a memory map of bits. Each bit is uniquely associated with a respective redial key and a respective memory bank of the arrangement. Each memory bank has a capacity sufficient to store a telephone number. Actuation of a predefined one of the redial keys always results in redialling of the last telephone number stored. If one of the other redial keys is actuated after telephone dialling, a memory management unit of the arrangement assigns a first value to the bit uniquely associated with that key and an available memory bank. Subsequent actuation of that other key then results in automatic redialling of the telephone number associated with that key. In a further form of the invention, one of the other redial keys may be actuated during, rather than after, dialling of the telephone number.

Abstract: A dial tone detector is provided possessing a precise definition of a passband. In one example, virtually infinite roll off is achieved in less than 5 hertz. An incoming analog signal of at least a predetermined amplitude is limited to produce square wave pulses which are counted in a first counter over a period of time determined by a periodic RESET signal. A READ signal occuring just before the RESET signal causes either a valid count state or an invalid count state to be stored depending upon the value of the count in the first counter. When a valid count state is in storage, a second counter counts timing pulses while the valid count state persists, whereby in the second counter a count of greater than a predetermined number indicates the presence of dial tone.

Abstract: The idle channel for a speech encoder is detected by the detection, at the encoder comparator output, of zero-level traversals caused by noise transient signals appearing at the analog input of the encoder. In response to the detection of an idle channel, the encoder is caused to output a PCM code sample corresponding to a zero amplitude analog signal. In order that a speech signal passing through zero amplitude during the sampling period not be confused with an idle channel condition, the detection circuit responds only to a plurality of zero-level traversals.