Abstract: Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors. In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106. In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region.

Abstract: Conductive elements which provide interconnections (air bridges between circuits) and components such as capacitors and inductors may be incorporated in the devices in a manner to reduce parasitic effects in the operation of the devices while providing close spacing which enhances the performance of the devices at high frequency. Separate substrates are provided respectively having the integrated circuits formed therein and covering, preferably sealing the integrated circuits. The air bridge conductive components (interconnections, capacitors or inductors) are formed separately in the covering substrate which is assembled with the substrate having the integrated circuit as a lid which seals and packages the circuits and the conductive element or component contained in the lid. The conductive component may be separated by cavities formed in the lid substrate or in the substrate having the integrated circuit device already formed therein.

Abstract: Semiconductor-on-glass integrated circuits may include photodetectors which are stimulated by backside light passing through the glass substrate; this provides information reception by optical communication. Bipolar and field effect transistors are shielded from the light by their buried layers. Further, LEDs integrated together with photodetectors permits all optical communication among glass substrate chips. Alternative uses of glass substrate include thermal isolation for efficient thermally regulated integrated circuits.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: Semiconductor-on-glass integrated circuits may include photodetectors which are stimulated by backside light passing through the glass substrate; this provides information reception by optical communication. Bipolar and field effect transistors are shielded from the light by their buried layers. Further, LEDs integrated together with photodetectors permits all optical communication among glass substrate chips. Alternative uses of glass substrate include thermal isolation for efficient thermally regulated integrated circuits.

Abstract: A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

Abstract: A silicon on insulator substrate 8 provides islands of silicon 18 of uniform thickness by using a trench etch process and a silicon nitride layer 20 to provide a thickness control and polish stop for the silicon islands 18.

Abstract: Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

Abstract: Methods of forming a carbon containing, minority carrier barrier layer on the surface of a semiconductor, which methods may be used to form barriers between the emitter of a single crystal transistor and a polysilicon layer in electrical contact therewith, and thus transistors with an emitter with enhanced efficiency.

Abstract: Recessed isolation oxide is deposited in shallow trenches simultaneoulsy with oxide deposition in deep isolation trenches. A single planarization of both trench fillings provides efficient recessed isolation oxide without bird's beak or bird 's head problems of LOCOS isolation oxide. Self-aligned trench filling by successive conformal depositions of oxide and polysilicon followed by planarization to remove polysilicon away from the trenches. The the remaining polysilicon may be used as an oxide etch mask to remove all of the oxide except in the trenches.

Abstract: A double level conductive structure is provided wherein one conductor layer permits impurities to pass therethrough in a given impurity introduction steph while double conductor level portion substantially prevents such impurities from passing therethrough due to a greater combined resistance to impurity penetration.

Abstract: Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

Abstract: A compact vertical contact has lateral space requirements in the fabrication of semiconductor devices and is compatible with highly planarized processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer may be contacted at an edge rather than on its top surface in order to reduce the lateral expanse of the contact.

Abstract: Integrated circuits with vertical isolated trenches are radiation hardened by providing vertical gate segments, preferably, of doped polycrystalline silicon, in the trenches and connected at the bottom of the trenches to a region of the same conductivity type. The surface devices may be complementary and the vertical gates may also be complementarily doped. A method of fabrication is described for a single crystal wafer, as well as SOI.

Abstract: A process for the formation of a compact vertical contact having reduced lateral space requirements yet compatible with highly planarized semiconductor manufacturing processes. The contact is made from a foundation region having a top surface to an overlying layer separated from the foundation region by a dielectric. The overlying layer can be contacted on its edge rather than on its top surface in order to reduce the lateral expanse of the contact.

Abstract: A protection circuit including complementary bipolar transistors having collectors connected to an input and base and emitters connected together to a respective voltage source. The bipolar transistors are lateral transistors having a field plate over the base region and spaced laterally from the laterally spaced collector and emitter regions. The base may include increased impurity surface regions extending from the emitter and collector to the gate to increase the beta and decrease the collector-base breakdown.

Abstract: Photoresist apertures having tapered sidewalls can be provided by first opening the aperture in accordance with ordinary practice followed by the exposure of the photoresist to a suitable energy source such as a flood exposure to wideband light, the heating of the photoresist to round the peripheral edges of the aperture and the exposure of the thus pretreated photoresist to an environment which removes photoresist from the inside wall of the aperture until the desired tapered profile is obtained. In the preferred practice of the invention, the pretreated photoresist is removed from the inside wall of the aperture through exposure to a dry oxygen plasma etch.

Abstract: A method is provided for semiconductor manufacture wherein a via is defined and etched through an insulative layer of the device to an underlying conductive region and metal fillets are formed in the corner regions of the via. A conformal metal layer is then deposited onto the device and etched until all metal is removed from the insulative layer surface. Finally, a second metal interconnect layer is deposited onto the device and the desired interconnect pattern is defined. The fillets displace the metal subsequently deposited on the via side surface laterally toward the center of the via, thereby preventing severe self-shadowing problems and improving step coverage of metal into the via.

Abstract: A pattern for determining dimensions of projected or printed figures is provided having individual scaling figures therein on a mask or template. Dimensional measurement may be indicated by alignment of opposing edges of scaling figures offset from each other along the corresponding axis of alignment. Reference marks may be provided on the pattern and associated with each possible axis of alignment for indicating an absolute dimension of a concurrently projected or printed figure. To conserve space, the pattern may be "densepacked" with scaling figures such that each scaling figure includes a plurality of opposing edges, each alignable along a different axis in response to different levels of dimensional distortion.