Abstract: A transmitting element for generating a magnetic field for tracking of an object includes a first spiral trace that extends from a first outer origin inward to a central origin in a first direction. A second spiral trace can extend from the central origin outward to a second outer origin in the first direction. The second spiral trace can extend from the central origin to the second outer origin in the first direction. The first spiral trace and the second spiral trace can be physically connected at the central origin to form the fluorolucent magnetic transmitting element and at least a portion of the first spiral trace overlaps at least a portion of the second spiral trace.

Abstract: This disclosure describes a composition comprising an alkyl nitrite, such as isoamyl nitrite, and an effective amount of at least one stabilizing compound, such as one or more of vitamins K1, K2, and K3.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.

Abstract: An integrated circuit is provided with a set of sensors for scaling voltage based on performance of the integrated circuit. The set of sensors are monitored, and sensor provides an output value indicative of a performance metric of the integrated circuit. The output values from the set of sensors are combined using a calibrated model to determine when a threshold value is reached. A change to an operating voltage for a portion of the integrated circuit is initiated in response to reaching the threshold.

Abstract: An integrated circuit is provided with a set of sensors for scaling voltage based on performance of the integrated circuit. The set of sensors are monitored, and sensor provides an output value indicative of a performance metric of the integrated circuit. The output values from the set of sensors are combined using a calibrated model to determine when a threshold value is reached. A change to an operating voltage for a portion of the integrated circuit is initiated in response to reaching the threshold.

Abstract: This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.

Abstract: A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters of the active device elements. This approach provides an expectation of detection and elimination of noise hazards that might otherwise not be undetected.

Abstract: The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.

Abstract: An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

Abstract: In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.

Abstract: An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

Abstract: The invention is an energy efficient fully scannable D master-slave flip-flop circuit with synchronous preset or clear capability. The output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.

Abstract: A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below.

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic.