Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

Abstract: Methods and systems for generating a signature for a device include pre-charging a plurality of conductors to a first voltage level. A voltage leakage for each of the conductors is determined, and a device signature is generating based on the determined leakage.

Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

Abstract: Methods and systems for generating a signature for a device include pre-charging a plurality of conductors to a first voltage level. A voltage leakage for each of the conductors is determined, and a device signature is generating based on the determined leakage.

Abstract: An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.

Abstract: An integrated circuit (IC) comprises a first conductor in one layer of the IC, a second conductor in another layer of the IC, and a first metal plug connecting the first and second conductors. The IC further comprises an atomic source conductor (ASC) in the one layer of the IC and joined to the first conductor, and a second metal plug connecting the ASC to a voltage source of the IC. The first conductor and the ASC are configured to be biased to different voltages so as to establish an electron path from the second metal plug to the first metal plug such that the ASC acts as an active atomic source for the first conductor.

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract: This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.

Abstract: This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.

Abstract: Electrostatic discharge (ESD) protection in high voltage semiconductor devices is disclosed that provides enhanced current isolation between transistor drains or sources by creating an isolation island surrounding the drains or sources. This isolation island can be a higher-doped region within which the drain/source lies. The junction between the higher doping of this island region and the surrounding substrates operates to limit the amount of current that passes through the drain/source. Additionally, oxide features may be used to create an island surrounding the drain/source contact. Again, this isolating effect makes the amount of current passing through the device more uniform, which protects the device from damage due to an ESD event.

Abstract: A method and system for a high current semiconductor memory cell provides a semiconductor memory cell with two current carrying structures. At least one of the current carrying structures is segmented and formed of narrow wire segments from one or more levels coupled to wider connective squares of another level. The wire segments may be a conductive material and the connective squares a refractory material. The short length wire segments may include a length less than the average grain size of the material of which they are formed.

Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

Abstract: An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

Abstract: A method and system for a high current semiconductor memory cell provides a semiconductor memory cell with two current carrying structures. At least one of the current carrying structures is segmented and formed of narrow wire segments from one or more levels coupled to wider connective squares of another level. The wire segments may be a conductive material and the connective squares a refractory material. The short length wire segments may include a length less than the average grain size of the material of which they are formed.

Abstract: This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.

Abstract: This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.