Patents by Inventor Anthony Pang

Anthony Pang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9483494
    Abstract: Opportunistic repair of fragmentation in a synthetic backup is disclosed. In various embodiments, data generated to perform processing other than fragmentation repair is received. At least a portion of the received data is used to compute a locality measure with respect to a group of segments comprising a portion of a file. A decision whether to repair fragmentation of segments comprising the group is made based at least in part on the computed locality measure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 1, 2016
    Assignee: EMC Corporation
    Inventors: Hung Hing Anthony Pang, Fabiano Botelho, Dhanabal Ekambaram, Nitin Garg
  • Patent number: 9405761
    Abstract: Exemplary methods for verifying data integrity for garbage collection with limited memory include maintaining a data structure that includes a plurality of entries, storing states of a group of segments compressed therein. In response to receiving a request for transitioning a segment from a first state to a second state, retrieving a first entry value of an entry associated with the first segment, generating a second entry value based on the first entry value, the first state, the second state, and a value obtained from a first lookup table based on the first segment. The methods also include writing back the second entry value to the first entry of the data structure. In one embodiment, in response to determining all entries of the data structure reach a predetermined final state, performing a garbage collection process on the segments stored in the storage system.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: August 2, 2016
    Assignee: EMC Corporation
    Inventors: Fabiano C. Botelho, Hung Hing (Anthony) Pang
  • Patent number: 9367448
    Abstract: A garbage collector of a storage system traverses a namespace of a file system of the storage system to verify data integrity of segments. The namespace identifies files that are represented by segments arranged in multiple levels in a hierarchy, where an upper level segment includes one or more references to one or more lower level segments, and at least one segment is referenced by multiple files. Traversing the namespace includes computing and verifying checksums all segments in a level-by-level manner, where checksums of an upper level are verified before any of checksums of a lower level are verified. Upon all checksums of all levels have been verified, a garbage collection process is performed on the segments stored in the storage system.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: June 14, 2016
    Assignee: EMC Corporation
    Inventors: Fabiano C. Botelho, Dheer Moghe, Hung Hing (Anthony) Pang, Guilherme Vale Ferreira Menezes
  • Publication number: 20160041907
    Abstract: Systems and methods for managing records stored in a storage cache are provided. A cache index is created and maintained to track where records are stored in buckets in the storage cache. The cache index maps the memory locations of the cached records to the buckets in the cache storage and can be quickly traversed by a metadata manager to determine whether a requested record can be retrieved from the cache storage. Bucket addresses stored in the cache index include a generation number of the bucket that is used to determine whether the cached record is stale. The generation number allows a bucket manager to evict buckets in the cache without having to update the bucket addresses stored in the cache index. Further, the bucket manager is tiered thus allowing efficient use of differing filter functions and even different types of memories as may be desired in a given implementation.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 11, 2016
    Inventors: Woon Ho Jung, Nakul Dhotre, Deepak Jain, Anthony Pang
  • Publication number: 20160034487
    Abstract: Selective repair of fragmentation in a synthetic backup, based at least in part on a dynamically-determined repair criteria, is disclosed. In various embodiments, a locality measure is computed with respect to a group of segments comprising a portion of a file. The computed locality measure is compared to an at least partly dynamically determined fragmentation repair criteria, and a repair decision is made based at least in part on the comparison.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Inventors: Hung Hing Anthony Pang, Fabiano Botelho, Dhanabal Ekambaram, Nitin Garg
  • Patent number: 9195672
    Abstract: Selective repair of fragmentation in a synthetic backup, based at least in part on a dynamically-determined repair criteria, is disclosed. In various embodiments, a locality measure is computed with respect to a group of segments comprising a portion of a file. The computed locality measure is compared to an at least partly dynamically determined fragmentation repair criteria, and a repair decision is made based at least in part on the comparison.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: EMC Corporation
    Inventors: Hung Hing Anthony Pang, Fabiano Botelho, Dhanabal Ekambaram, Nitin Garg
  • Patent number: 7571412
    Abstract: A method for generating automatic design characterization patterns for integrated circuits (IC) is provided. The method includes selecting a routing scheme from a file containing the device description of the routings of the IC. The routing scheme may be of a phase locked loop, clock tree, delay element, or input output block in one embodiment. Resource types for the routing scheme are identified and a path is defined, within constraints, between the resources. Once a path is defined, alternate paths are defined by retracing the path within constraints from an end of the path to the beginning of the path. An alternative path is then built and the alternative path shares a portion of the path previously defined. A computing system providing the functionality of the method is also provided.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: August 4, 2009
    Assignee: Altera Corporation
    Inventors: Hung Hing Anthony Pang, Binh Vo, Souvik Ghosh
  • Patent number: 7103813
    Abstract: A bridging fault detection system allows for a high amount of test coverage using a low number of test configurations. The bridging fault detection system automatically creates optimal test configurations and test vectors without the need for precise layout information, and is adaptable to complex programmable device architectures. Testers can specify a precise level of testing coverage to optimize the testing processing. A programmable device with interconnect bias circuitry decreases the number of test configurations and thus the time needed to test for bridging faults. The interconnect bias circuit provides explicit test control over the unused lines in a configuration, driving them both high and low for complete test coverage between each line and all of its possible neighbors. The bridging fault detection system balances the available number of control test points against the number of interconnect segments stitched together by programmable connection to maximize the lines under test per configuration.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: September 5, 2006
    Assignee: Altera Corporation
    Inventors: Paul Tracy, Anthony Pang, Andy Lee, Adam Wright, Rahul Saini
  • Patent number: 7024327
    Abstract: Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: April 4, 2006
    Assignee: Altera Corporation
    Inventors: Jayabrata Ghosh Dastidar, Adam Wright, Hung Hing Anthony Pang, Binh Vo, Ajay Nagarandal, Paul J. Tracy, Michael Harms