Abstract: A phase- or frequency-locked loop circuit (200) that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (148, 304A, 304B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector (216) and a glitch detector (208) that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.

Abstract: A method for managing power consumptions of a sending driver and a receiving driver within a data communication system is disclosed. The sending driver is coupled to a sender and a sensor. The receiving driver is coupled to a receiver and a controller. The sensor adjusts a transmission frequency and a supply voltage level to the sending driver according to the amount of data that needed to be sent by the sender. Data within the sender are then transmitted by the sending driver to the receiving driver according to the adjusted transmission frequency and the adjusted supply voltage level.

Abstract: An asynchronous data transfer interface is provided across a boundary that allows high bandwidth data transfers which are packet based as defined by PCI_Express architecture, and has general utility in processor-based applications like servers, desktop applications, and mobile applications. A shared set of multi-port RAM buffers allow both an application layer AL and a transaction layer TL access to a communication protocol layer in a defined process that allows both the application layer AL and the transaction layer TL to read and manage the buffers in a 16 byte boundary in a manner that allows a data credit to be decoupled from a header credit.