Patents by Inventor Anthony Peter John Claydon
Anthony Peter John Claydon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150172215Abstract: An apparatus for providing a bridge between a plurality of devices and a network, the apparatus comprising: one or more device interfaces, arranged to provide a physical interface between the apparatus and said plurality of devices; one or more device adaptors, each device adaptor connected to one of said one or more device interfaces, and arranged to send and/or receive data to and/or from at least one of said plurality of devices; one or more apps, each app arranged to connect to at least one of said one or more device adaptors via one or more sockets, and arranged to send and/or receive said data to and/or from said at least one of said one or more device adaptors via the one or more sockets; and an apparatus controller arranged to receive permissions from a remote server over an external interface and establish said sockets based on said permissions.Type: ApplicationFiled: December 18, 2014Publication date: June 18, 2015Inventors: Anthony Peter John Claydon, Martin William Sotheran
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Patent number: 8904148Abstract: There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus.Type: GrantFiled: July 5, 2011Date of Patent: December 2, 2014Assignee: Intel CorporationInventors: Anthony Peter John Claydon, Anne Patricia Claydon
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Patent number: 8386752Abstract: A processor architecture includes a plurality of processing elements and a bus structure. Each element has at least one input port and at least one output port, each port having at least a data bus and a valid data signal line. The bus structure contains a plurality of switches arranged to connect an output port of any first processing element to the input port of any second processing element for a time interval. Each processing element sets a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value and to a second logic state when it does not contain a transfer value. Each processing element enters a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state.Type: GrantFiled: October 19, 2001Date of Patent: February 26, 2013Assignee: Mindspeed Technologies U.K., LimitedInventor: Anthony Peter John Claydon
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Publication number: 20120191945Abstract: There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus.Type: ApplicationFiled: July 5, 2011Publication date: July 26, 2012Inventors: Anthony Peter John Claydon, Anne Patricia Claydon
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Patent number: 7996652Abstract: A processor architecture includes a plurality of elements arranged in an array of rows and columns and a plurality of first and second bus pairs with the first pair being located between different adjacent rows of the array and having first and second buses running in opposite directions and the second bus pair being located between different adjacent columns of the array and having third and fourth buses running in opposite directions and intersecting the first and second buses. A plurality of switch matrices located at an intersection of one of the first bus pairs and one of the second bus pairs includes inputs and outputs for first, second, third and fourth buses and switch elements for switchably connecting the inputs and outputs.Type: GrantFiled: February 21, 2008Date of Patent: August 9, 2011Inventors: Anthony Peter John Claydon, Anne Patricia Claydon
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Patent number: 7987340Abstract: Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.Type: GrantFiled: February 19, 2004Date of Patent: July 26, 2011Inventors: Gajinder Panesar, Anthony Peter John Claydon, William Philip Robbins, Alex Orr, Andrew Duller
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Patent number: 7549081Abstract: An array of processing elements can incorporate a degree of redundancy. Specifically, the array includes one or more spare, or redundant, rows of array elements, in addition to the number required to implement the intended function or functions of the device. If a defect occurs in one of the processors in the device, then the entire row which includes that defective processor is not used, and is replaced by a spare row.Type: GrantFiled: June 27, 2003Date of Patent: June 16, 2009Assignee: picoChips Design LimitedInventors: William Robbins, Michael Davison, Simon Howell, Anthony Peter John Claydon
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Publication number: 20080222339Abstract: There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus.Type: ApplicationFiled: February 21, 2008Publication date: September 11, 2008Inventors: Anthony Peter John Claydon, Anne Patricia Claydon
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Patent number: 6910125Abstract: A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number.Type: GrantFiled: February 6, 2001Date of Patent: June 21, 2005Assignee: Discovision AssociatesInventors: Adrian P. Wise, Martin W. Sotheran, William P. Robbins, Anthony M. Jones, Anthony Peter John Claydon, Kevin Boyd, Helen R. Finch
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Publication number: 20040078548Abstract: There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs,each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus.Type: ApplicationFiled: November 21, 2003Publication date: April 22, 2004Inventors: Anthony Peter John Claydon, Anne Patricia Claydon
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Patent number: 6154871Abstract: The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data.Type: GrantFiled: November 14, 1997Date of Patent: November 28, 2000Assignee: Discovision AssociatesInventors: Anthony Peter John Claydon, Richard John Gammack, William Philip Robbins, Charles Dunlop MacFarlane, Thomas Foxcroft, Andrew Peter Kuligowski, Richard James Thomas
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Patent number: 5984512Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in select stages and are responsive to a recognized control token for reconfiguring such stages to handle an identified DATA Token. A wide variety of unique supporting subsystems circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: November 16, 1999Assignee: Discovision AssociatesInventors: Anthony Mark Jones, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5953311Abstract: A method and apparatus are disclosed for determining the boundaries of guard intervals of data symbols being received in a coded orthogonal frequency division multiplexed signal. Temporal samples separated by an interval of an active interval of a data symbol are associated in pairs, and difference signals obtained. The dispersion of a first comparison block of difference signals is determined, and compared to the dispersion of a second comparison block of difference signals, the second comparison block being displaced from the first comparison block by n samples. An F ratio is calculated for the dispersions of the two blocks. F ratios are iterated in a succession of comparison blocks, and a signal representing the F ratios subjected to peak detection. The peaks represent the boundaries of the symbol's guard interval. This information is utilized in synchronizing an FFT window for subsequent signal reconstruction.Type: GrantFiled: February 18, 1997Date of Patent: September 14, 1999Assignee: Discovision AssociatesInventors: David Huw Davies, Jonathan Parker, Anthony Peter John Claydon
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Patent number: 5835792Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: November 10, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5829007Abstract: A RAM implementation of asynchronous swing buffering is provided in which two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a fast rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer.Type: GrantFiled: June 7, 1995Date of Patent: October 27, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5821885Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: October 13, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5805914Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.Type: GrantFiled: June 7, 1995Date of Patent: September 8, 1998Assignee: Discovision AssociatesInventors: Adrian Philip Wise, Martin William Sotheran, William Philip Robbins, Anthony Peter John Claydon, Kevin James Boyd, Helen Rosemary Finch
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Patent number: 5768629Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: June 16, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes
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Patent number: 5742622Abstract: The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data.Type: GrantFiled: April 26, 1996Date of Patent: April 21, 1998Assignee: Discovision AssociatesInventors: Anthony Peter John Claydon, Richard John Gammack, William Philip Robbins, Charles Dunlop MacFarlane, Thomas Foxcroft, Andrew Peter Kuligowski, Richard James Thomas
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Patent number: 5740460Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.Type: GrantFiled: June 7, 1995Date of Patent: April 14, 1998Assignee: Discovision AssociatesInventors: Adrian P. Wise, Kevin D. Dewar, Anthony Mark Jones, Martin William Sotheran, Colin Smith, Helen Rosemary Finch, Anthony Peter John Claydon, Donald William Patterson, Mark Barnes, Andrew Peter Kuligowski, William P. Robbins, Nicholas Birch, David Andrew Barnes