Abstract: The present disclosure relates to a network chip (108) comprising: a programmable infrastructure (201) having a plurality of access points (202); at least one chiplet communications interface (3D PLUG) suitable for interfacing with at least one chiplet (110), each chiplet communications interface (3D PLUG) being coupled to a corresponding one of the access points (202); and a plurality of network-to-network communications interfaces (206, 208, 210, 212) each suitable for interfacing with another network chip (108).

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.

Abstract: This system for processing digital data may include a set of slave processing units for the execution of elementary functions, an interconnection module, which is designed to communicate with a data transfer network and to transfer data between the processing units, on the one hand, and the data transfer network, on the other hand, and a controller controlling the interconnection module to control the data transfer.

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing of data from the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.

Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.

Abstract: A method is provided for managing access to a ring buffer, for at least one data transfer channel for a determined amount of data, with this ring buffer comprising a series of buffer sub-areas spaced apart by a memory address offset and ordered from a first buffer sub-area to a last buffer sub-area. A starting address is initialized from a first register storing the value of the memory address of the first buffer sub-area, and a counter is initialized from a second register storing the value of the number of buffer sub-areas in the buffer. The buffer sub-areas are successively accessed, from the first buffer sub-area to the last buffer sub-area, starting from the starting address and as a function of the memory address offset, on the basis of the value of the counter. The initialization and access steps are repeated such that the determined amount of data is transferred.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.

Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing device with the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.