Abstract: A wireless communication transmitter (200) configured to segment a transport block into C segments, encode each segment into a set of encoded bits, determine, for ? encoded segments, a subset of size M0? of encoded bits for each encoded segment and for C?? encoded segments, a subset of size M1? of encoded bits for each encoded segment, wherein the subset sizes M0? and M1? differ at most by P bits, where P is a product of a modulation order and a number of transmission layers over which the transport block is transmitted. The selected subsets of encoded bits are concatenated and grouped to form modulation symbols of the modulation order.

Abstract: Methods and apparatus for estimating time of arrival information associated with a wireless signal are disclosed. In an embodiment, a wireless device (102), or any other suitable device or system, determines a channel type based on multiple occurrences of a reference signal (700) (e.g., determine if a channel is delay-spread or non-delay-spread based on a ratio of largest peak to a mean of other peaks). The wireless device (102) then selects a time of arrival generator (800 or 900) based on the channel type (e.g., use delay-spread estimator if ratio is below threshold, and use non-delay-spread estimator if ratio is above threshold). The wireless device then (102) estimates the time of arrival information using the selected time of arrival generator (800 or 900) (e.g., sum peaks from multiple occasions and then estimate for delay-spread or estimate the time of arrival from each occasion and then average for non-delay-spread).

Abstract: Methods and apparatus for estimating time of arrival information associated with a wireless signal are disclosed. In an embodiment, a wireless device (102), or any other suitable device or system, determines a channel type based on multiple occurrences of a reference signal (700) (e.g., determine if a channel is delay-spread or non-delay-spread based on a ratio of largest peak to a mean of other peaks). The wireless device (102) then selects a time of arrival generator (800 or 900) based on the channel type (e.g., use delay-spread estimator if ratio is below threshold, and use non-delay-spread estimator if ratio is above threshold). The wireless device then (102) estimates the time of arrival information using the selected time of arrival generator (800 or 900) (e.g., sum peaks from multiple occasions and then estimate for delay-spread or estimate the time of arrival from each occasion and then average for non-delay-spread).

Abstract: The present invention discloses a method and apparatus for wide dynamic range phase conversion. In one embodiment, inphase and quadrature signal components of a complex input signal are collapsed into a single quadrant to produce a first signal representation. A scaling operation is subsequently performed on the first signal representation to produce a second signal representation. Lastly, the second signal representation is converted into the phase domain.

Abstract: A noise thresholder of a baseband modem integrated circuit (BMIC) compares measured noise variances on corresponding receiver paths to a pre-established threshold minimum value. The noise thresholder assigns as a noise variance value for a corresponding receiver path either (a) a measured noise variance value for each receiver path having a measured noise variance that is larger than the pre-established threshold minimum, and (b) the pre-established threshold minimum value for each receiver path having a measured noise variance that is less than or equal to the pre-established threshold minimum value. A noise balancer performs noise balancing to provide a same signal to noise ratio (SNR) across all receiver paths, based on the assigned noise variances provided at the noise thresholder. A detection engine utilizes a lowest assigned noise variance value and outputs yielded by the noise balancer to simplify equalization computations while providing a high performance symbol detection capability.

Abstract: A noise thresholder of a baseband modem integrated circuit (BMIC) compares measured noise variances on corresponding receiver paths to a pre-established threshold minimum value. The noise thresholder assigns as a noise variance value for a corresponding receiver path either (a) a measured noise variance value for each receiver path having a measured noise variance that is larger than the pre-established threshold minimum, and (b) the pre-established threshold minimum value for each receiver path having a measured noise variance that is less than or equal to the pre-established threshold minimum value. A noise balancer performs noise balancing to provide a same signal to noise ratio (SNR) across all receiver paths, based on the assigned noise variances provided at the noise thresholder. A detection engine utilizes a lowest assigned noise variance value and outputs yielded by the noise balancer to simplify equalization computations while providing a high performance symbol detection capability.

Abstract: A method for improving burst acquisition in a receiver includes receiving a signal, and performing a sync word search on the signal, wherein the sync word search includes performing a hybrid synchronization technique, the hybrid synchronization technique including both a lower order modulation (e.g., BPSK) detection and correlation process and a higher order modulation (e.g., QPSK) detection and correlation process.

Abstract: A wireless communication transmitter (200) configured to segment a transport block into C segments, encode each segment into a set of encoded bits, determine, for ? encoded segments, a subset of size M0? of encoded bits for each encoded segment and for C?? encoded segments, a subset of size M1? of encoded bits for each encoded segment, wherein the subset sizes M0? and M1? differ at most by P bits, where P is a product of a modulation order and a number of transmission layers over which the transport block is transmitted. The selected subsets of encoded bits are concatenated and grouped to form modulation symbols of the modulation order.

Abstract: A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.

Abstract: An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.

Abstract: A programmable correlator for a communication system includes an input queue coupled with an analog-to-digital converter (ADC). The input queue includes a random access memory (RAM) wherein sampled data streams from the ADC are written into the RAM. The input queue has two banks of memory of width 2M. A flexible complex correlator is operable on M samples. The correlator is coupled to read M complex samples out of 2M samples from the input queue. A pseudo-noise (PN) crossbar unit operates to rotate a generated PN code to match a rotation of the input queue data in the complex correlator.

Abstract: A programmable correlator for a communication system includes an input queue coupled with an analog-to-digital converter (ADC). The input queue includes a random access memory (RAM) wherein sampled data streams from the ADC are written into the RAM. The input queue has two banks of memory of width 2M. A flexible complex correlator is operable on M samples. The correlator is coupled to read M complex samples out of 2M samples from the input queue. A pseudo-noise (PN) crossbar unit operates to rotate a generated PN code to match a rotation of the input queue data in the complex correlator.

Abstract: A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.

Abstract: A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.

Abstract: A signaling mechanism for sending and receiving signals to and from any one of all of a plurality of devices, including peripheral controllers and processors, in a multiprocessor system. The signaling mechanism includes two switches, a first switch routing a signal command generated by the device to a signal dispatch logic and a second switch for receiving signals generated by the signal dispatch logic and routing the signals to the selected device. The signal dispatch logic receiving the signal command, decodes the destination select value and generates a signal to be sent to the selected device. The signal command includes a destination select value representing a device selectably determined by the device. The signaling mechanism also includes an arbitration mechanism connected to the signal dispatch logic and the first switch for resolving simultaneous conflicting signal commands issued by two or more devices.

Abstract: A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.

Abstract: Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.