Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: A method of programming a FPGA, wherein the FPGA comprises an array of macrocells, each comprising at least a configurable hardware block and a configurable interconnection network, the method comprises the steps of: providing a high-level configuration file containing: first data defining a set of macrocells and their relative positions; second data defining a configuration of the hardware blocks of the macrocells; and third data defining interconnections between the macrocells; wherein said high-level configuration file contains neither data defining an absolute position of the macrocells within the FPGA, nor local routing information fully defining a configuration of their interconnection networks; converting said high-level configuration file into a bitstream file; and uploading the bitstream file into the FPGA. A semiconductor chip comprising a FPGA and a device configured for programming the FPGA are provided.

Abstract: An encoder comprises a first and a second input, and a first and a second output, and the encoder comprises a selection block suitable for selecting a more significant bit and a less significant bit. The encoder comprises a switching block suitable for connecting the first input to the first output, and the second input to the second output, the switching block being suitable for being switched in order to connect the first input to the second output and the second input to the first output, when the selection block has selected a less significant bit and a more significant bit. A decoder, a storage medium and an electronic system is also disclosed.

Abstract: The invention relates to an encoder (2) comprising a first (4) and a second (14) input, and a first (6) and a second (16) output, the encoder (2) comprising a selection block (24, 26, 28) suitable for selecting a more significant bit and a less significant bit. The encoder (2) comprises a switching block (44, 46) suitable for connecting the first input (4) to the first output (6), and the second input (14) to the second output (16), the switching block (44, 46) being suitable for being switched in order to connect the first input (4) to the second output (16) and the second input (14) to the first output (6), when the selection block (24, 26, 28) has selected a less significant bit and a more significant bit. The invention relates also to a decoder, a storage medium and an electronic system.