Abstract: The present disclosure generally relates to a conductive perforated plate for electrical testing of a device under test (DUT) in semiconductor processing. In an example, a device circuit in a die area is formed in or over a semiconductor substrate. The device circuit has an interconnect level. A DUT is formed in or over the semiconductor substrate. A conductive perforated plate is formed in the interconnect level conductively connected to the DUT. A plurality of insulating islands is disposed within the conductive perforated plate.

Abstract: In examples, a semiconductor package comprises a bond pad surface layer, a second conductive layer positioned below the bond pad surface layer, and a perforated plate positioned between and abutting the bond pad surface layer and the second conductive layer. The perforated plate has a monolithic conductive member and multiple insulation members embedded within the conductive member, the insulation members having thicknesses approximately equivalent to that of the conductive member. The package also includes a semiconductor substrate including a circuit, the semiconductor substrate positioned below the second conductive layer.