Patents by Inventor Anton Pelteshki
Anton Pelteshki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9405511Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: GrantFiled: October 27, 2014Date of Patent: August 2, 2016Assignees: STMICROELECTRONICS (CANADA) INC., STIMICROELECTRONICS S.R.L.Inventors: John Hogeboom, Hock Khor, Matteo Alessio Traldi, Anton Pelteshki
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Publication number: 20150074160Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: ApplicationFiled: October 27, 2014Publication date: March 12, 2015Inventors: JOHN HOGEBOOM, HOCK KHOR, MATTEO ALESSIO TRALDI, ANTON PELTESHKI
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Patent number: 8886694Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: GrantFiled: December 22, 2011Date of Patent: November 11, 2014Assignees: STMicroelectronics (Canada) Inc., STMicroelectronics S.R.L.Inventors: John Hogeboom, Hock Khor, Matteo Traldi, Anton Pelteshki
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Patent number: 8866514Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.Type: GrantFiled: November 12, 2013Date of Patent: October 21, 2014Assignee: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, Hock Khor
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Patent number: 8754682Abstract: A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.Type: GrantFiled: April 18, 2012Date of Patent: June 17, 2014Assignee: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, Pat Hogeboom-Nivera
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Patent number: 8731041Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.Type: GrantFiled: April 18, 2012Date of Patent: May 20, 2014Assignee: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, John Hogeboom
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Publication number: 20140077845Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.Type: ApplicationFiled: November 12, 2013Publication date: March 20, 2014Applicant: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, Hock Khor
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Patent number: 8587348Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.Type: GrantFiled: December 21, 2011Date of Patent: November 19, 2013Assignee: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, Hock Khor
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Publication number: 20130002311Abstract: A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.Type: ApplicationFiled: December 21, 2011Publication date: January 3, 2013Applicant: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, Hock Khor
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Publication number: 20120269255Abstract: A DFE filter includes an input, a first filter loop coupled to the input for providing an odd bit-stream, and a second filter loop coupled to the input for providing an even bit-stream, wherein the first and second filter loops are identical and interleaved.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicant: STMicroelectronics (Canada) Inc.Inventors: Anton Pelteshki, John Hogeboom
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Publication number: 20120268177Abstract: A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.Type: ApplicationFiled: April 18, 2012Publication date: October 25, 2012Applicant: STMicroelectronics (Canada) Inc.Inventors: John Hogeboom, Pat Hogeboom-Nivera, Anton Pelteshki
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Publication number: 20120166505Abstract: A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Applicants: STMicroelectronics Srl, STMicroelectronics (Canada) Inc.Inventors: John Hogeboom, Hock Khor, Matteo Traldi, Anton Pelteshki