Abstract: The present invention corresponds to a gas cooling and condensing system using fluid energy and comprising a gas feed line, a first vortex tube connected to the gas feed line, a second vortex tube connected to the first vortex tube and a first heat exchanger connected to the second vortex tube and to the gas feed line. Said gas cooling and condensing system is a modular system, which may be replicated and connected in series or in parallel to another modular system to obtain a cooler or higher mass flow gas than that obtained with a single modular system. Moreover, the system of the present invention is optionally connected to thermal recovery, pressure recovery, recirculation or venting elements for the utilization of the waste gas streams. Furthermore, the system of the present invention does not require additional energy to that obtained from the pressure of the feed line for obtaining liquefied gas.

Abstract: A support device including a plurality of cells, each cell being at least partially defined by a cell wall, a chamber, and a plurality of valves. Each valve is movable between an open position where the valve provides fluid communication between an associated cell and the chamber, and a closed position wherein the valve generally blocks fluid communication between the associated cell and the chamber. Each valve is configured to be biased to a closed position during use of the device. The device is configured such that when a predetermined force is applied to each cell during use the associated valve moves to the open position.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal Fat the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: Methods and systems for measuring available direct memory access (DMA) throughput are disclosed, including providing a plurality of DMA channels, the DMA channels comprising a measuring DMA channel and other DMA channels, the measuring DMA channel having a lowest data rate priority, and determining an available DMA throughput by measuring a current data rate at which the measuring DMA channel is serviced in response to initiating a data transfer on the measuring DMA channel.

Abstract: Methods and systems for measuring available direct memory access (DMA) throughput are disclosed, including providing a plurality of DMA channels, the DMA channels comprising a measuring DMA channel and other DMA channels, the measuring DMA channel having a lowest data rate priority, and determining an available DMA throughput by measuring a current data rate at which the measuring DMA channel is serviced in response to initiating a data transfer on the measuring DMA channel.

Abstract: The facility is comprised of an oven (8) fitted with rotating supports (3) disposed parallel to each other, upon which preformed tubes (11) rest and rotate, which are introduced from a feeder (14) where they are contained at room temperature for their homogeneous circumferential heating inside said oven (8). Additionally, transverse displacement means (5, 6) are disposed inside the oven (8) in order to facilitate the elevation and transverse displacement of the preformed tubes (11), in such a manner as to favour the progressive and uniform heating throughout the thickness of said preformed tubes (11). On the other hand, it features assemblies that generate heating currents (15, 10, 2) comprised of elements (15), fans (10) and deflectors (2) longitudinally distributed in sectors or quadrants inside the oven (8), for the purpose of heating and distributing the air over the preformed tubes (11).

Abstract: A digital camera includes a sensor (205) for sensing an image and producing a first signal. A Bayer pattern producer (210) is coupled to the sensor and structured to produce a Bayer pattern from the first signal. The Bayer pattern is then split (212) into separate color channels. A color interpolator (214) is structured to perform a modification on only one of the color channels produced by the splitter (212). A compressor (220) then compresses the interpolated and non-interpolated color channels into a compressed image. An output interface (226) facilitates remote transmission of the compressed image over a communication channel. This communication may be made over a network to a server that operates in conjunction with the digital camera to perform certain functions, like image processing, manipulation, storage and communication, as directed by a user of the digital camera.

Abstract: A digital camera includes a sensor (205) for sensing an image and producing a first signal. A Bayer pattern producer (210) is coupled to the sensor and structured to produce a Bayer pattern from the first signal. The Bayer pattern is then split (212) into separate color channels. A color interpolator (214) is structured to perform a modification on only one of the color channels produced by the splitter (212). A compressor (220) then compresses the interpolated and non-interpolated color channels into a compressed image. An output interface (226) facilitates remote transmission of the compressed image over a communication channel. This communication may be made over a network to a server that operates in conjunction with the digital camera to perform certain functions, like image processing, manipulation, storage and communication, as directed by a user of the digital camera.

Abstract: A heat pump system based on the Peltier effect, built around a transparent or translucent material element and formed by two sheets (1) in which chains of thermoelements (3, 4) are embedded, trapped or inserted, said thermoelements being connected along their respective alternate ends with the aid of parts (2) made of a material with good thermal and electric conductivity properties, which chains are liable of being supplied with external electric energy so that heat transport is based on the direction of the current flowing through said thermoelements.