Patents by Inventor Antonio Jr B DIMAANO

Antonio Jr B DIMAANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor packages and methods of packaging semiconductor devices
    Patent number: 9881863
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 30, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • Semiconductor packages and methods of packaging semiconductor devices
    Patent number: 9589875
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: March 7, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
    Publication number: 20150380346
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 31, 2015
    Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
  • Semiconductor packages and methods of packaging semiconductor devices
    Patent number: 9136142
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: September 15, 2015
    Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
    Publication number: 20140227832
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Application
    Filed: April 21, 2014
    Publication date: August 14, 2014
    Applicant: United Test and Assembly Center Ltd.
    Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
  • Semiconductor packages and methods of packaging semiconductor devices
    Patent number: 8716873
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: May 6, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
  • SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
    Publication number: 20120001306
    Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 5, 2012
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG