Patents by Inventor Antonio M. Martinez

Antonio M. Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135402
    Abstract: A method can include establishing, by a computing system, a secure electronic network connection to an electronic agent running configured to access the dataset to dynamically generate the metadata related to the dataset on a client computing system. A method can include receiving, by the computing system, from the electronic agent via the secure electronic network connection, metadata related to a dataset, the metadata comprising a plurality of attributes of the dataset and a summary of the dataset. A method can include applying a valuation model to the metadata to determine an estimated value of the dataset, the valuation model comprising a machine learning model trained using marketplace data comprising sales prices and attributes of one or more datasets, wherein the model is trained to output the sales prices of the one or more datasets. A method can include determining, an estimated value of the dataset.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Lauren S. Cascio, Charles E. Fisher, Christopher M. Ensey, Michael S. Sobeck, Michael S. Blake, Gbolahan Promise Dada, Luis A. Obregon Mogollon, Rogfel Thompson Martínez, Antonio Martin Martinez, Carlos Valenzuela Lembach
  • Patent number: 4760290
    Abstract: In the present invention, an improved synchronous PLA circuit is disclosed. The PLA circuit is responsive to a single clock cycle. The PLA circuit has no internal or output glitches. Further, the PLA circuit uses less power since there are no internal or output glitches. The PLA circuit requires less area since metal lines do not have to carry as much power and do not have to be as wide as the prior art PLA circuits. Since less power is used, long term reliability is improved due to reduced heating stress and reduced current density stress (metal electromigration, etc.). The PLA circuit consists of two logic arrays and four dummy signal delay lines. When a clock signal gates the input signals into the logic array, it also simultaneously generates a dummy signal. The dummy signal propagates through adjacent dummy signal delay lines that parallel each logic array dimension and match the longest or worst case, delay through the logic array.
    Type: Grant
    Filed: May 21, 1987
    Date of Patent: July 26, 1988
    Assignee: VLSI Technology, Inc.
    Inventor: Antonio M. Martinez