Patents by Inventor Antonio R. Pelella
Antonio R. Pelella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8638595Abstract: A global to local bit line interface circuit for domino static random access memory (SRAM) devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with write data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and write-around logic configured to directly couple the write data presented on the complementary global write bit lines to read data output circuitry associated with the complementary global read bit lines.Type: GrantFiled: April 16, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventor: Antonio R. Pelella
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Publication number: 20130272057Abstract: A global to local bit line interface circuit for domino static random access memory (SRAM) devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with write data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and write-around logic configured to directly couple the write data presented on the complementary global write bit lines to read data output circuitry associated with the complementary global read bit lines.Type: ApplicationFiled: April 16, 2012Publication date: October 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Antonio R. Pelella
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Patent number: 8233331Abstract: A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.Type: GrantFiled: June 2, 2010Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Antonio R. Pelella, Richard E. Serton, Arthur Tuminaro
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Patent number: 8184475Abstract: An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs.Type: GrantFiled: February 15, 2010Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Antonio R. Pelella, Sudesh Saroop
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Publication number: 20110298500Abstract: A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.Type: ApplicationFiled: June 2, 2010Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen H. Chan, Antonio R. Pelella, Richard E. Serton, Arthur Tuminaro
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Publication number: 20110296259Abstract: A method of testing an integrated circuit device, the integrated circuit device having a memory array portion and a logic portion, includes providing test data to the memory array portion of the integrated circuit device using Array Built-In Self Test (ABIST) circuitry; and simultaneously testing the logic portion of the integrated circuit device using the ABIST circuitry, wherein both the memory array portion and the logic portion of the integrated circuit are tested at speed.Type: ApplicationFiled: May 26, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bargav Balakrishnan, Pradip Patel, Antonio R. Pelella, Daniel Rodko
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Publication number: 20110199817Abstract: An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs.Type: ApplicationFiled: February 15, 2010Publication date: August 18, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Antonio R. Pelella, Sudesh Saroop
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Patent number: 7592851Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.Type: GrantFiled: January 29, 2008Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ann H. Chen, Antonio R. Pelella, Shie-ei Wang
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Publication number: 20090189675Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.Type: ApplicationFiled: January 29, 2008Publication date: July 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen H. Chan, Ann H. Chen, Antonio R. Pelella, Shie-ei Wang
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Patent number: 7463537Abstract: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.Type: GrantFiled: November 1, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ryan T. Freese, Antonio R. Pelella, Arthur D. Tuminaro
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Patent number: 7336546Abstract: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.Type: GrantFiled: February 9, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ryan T. Freese, Antonio R. Pelella, Arthur D. Tuminaro
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Patent number: 7293209Abstract: A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2 is controlled to maintain a constant C2 duty cycle.Type: GrantFiled: February 9, 2005Date of Patent: November 6, 2007Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ryan T. Freese, Antonio R. Pelella
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Patent number: 7272030Abstract: A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.Type: GrantFiled: October 30, 2006Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ryan T. Freese, Antonio R. Pelella, Uma Srinivasan, Arthur D. Tuminaro, Jatinder K. Wadhwa
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Patent number: 7170774Abstract: A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.Type: GrantFiled: February 9, 2005Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ryan T. Freese, Antonio R. Pelella, Uma Srinivasan, Arthur D. Tuminaro, Jatinder K. Wadhwa
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Patent number: 7113433Abstract: A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently.Type: GrantFiled: February 9, 2005Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Ryan T. Freese, Antonio R. Pelella, Arthur D. Tuminaro
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Patent number: 7102946Abstract: Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is turned on by a timing pulse during the read operation, but only if the Array Built In Self-Test (ABIST) has detected a slow to read cell in the local group. If there is no slow cell, the amplifier is not activated, and the domino read operation is carried out. The amplifier can be used globally across the SRAM or selectively in certain sub-arrays.Type: GrantFiled: February 9, 2005Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventor: Antonio R. Pelella
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Patent number: 7084673Abstract: A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.Type: GrantFiled: May 12, 2004Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Antonio R. Pelella, Jatinder K. Wadhwa, Otto M. Wagner
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Patent number: 7054184Abstract: A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.Type: GrantFiled: May 12, 2004Date of Patent: May 30, 2006Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Timothy J. Charest, Antonio R. Pelella, John R. Rawlins
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Patent number: 6868000Abstract: A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.Type: GrantFiled: May 12, 2003Date of Patent: March 15, 2005Assignee: International Business Machines Corp.Inventors: Yuen H. Chan, Rajiv V. Joshi, Antonio R. Pelella
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Publication number: 20040228160Abstract: A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.Type: ApplicationFiled: May 12, 2003Publication date: November 18, 2004Inventors: Yuen H. Chan, Rajiv V. Joshi, Antonio R. Pelella