Abstract: A fixing system is disclosed for mounting a camera to a support structure. The fixing system comprises a mounting plate attachable to the support structure and a base detachably connectable to the mounting plate. The mounting plate includes a recess, and the base includes an index plunger with a pressure-loaded pin and a plunger head. When the base is connected to the mounting plate, the pressure-loaded pin of the index plunger is inserted in the recess of the mounting plate. Furthermore, the plunger head of the index plunger is accessible from a side of the base facing away from the mounting plate to pull the pressure-loaded pin out of the recess.

Abstract: The vehicular speed detection and warning system is a traffic safety device. The vehicular speed detection and warning system is configured for use with a vehicle. The vehicular speed detection and warning system is configured for use on a road network. The vehicular speed detection and warning system is configured for use with a road network. The road network further comprises one or more streets, traffic signs, and traffic signals. The control module monitors and logs the compliance of the vehicles with the traffic control information presented by the traffic signs and the traffic signals by capturing images of the traffic signs and the traffic signals and comparing the traffic control instructions provided by the traffic signs and traffic signals with the operating performance of the vehicle.

Abstract: Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion.

Abstract: Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion.

Abstract: Formula (I) and (II). The present invention relates to the use of a new lupane derivative of general formula (I) or (II), or a pharmaceutically acceptable salt, crystal form, complex, hydrate, or hydrolysable ester thereof, for preventing and/or inhibiting tumor growth and for treating cancer and other proliferative diseases, more particularly for treating leukemia, liver, cervical, colon and prostate cancer. The present invention also relates to the synthesis of these compounds and to pharmaceutical compositions which contain them.

Abstract: Formula (I) and (II). The present invention relates to the use of a new lupane derivative of general formula (I) or (II), or a pharmaceutically acceptable salt, crystal form, complex, hydrate, or hydrolysable ester thereof, for preventing and/or inhibiting tumor growth and for treating cancer and other proliferative diseases, more particularly for treating leukemia, liver, cervical, colon and prostate cancer. The present invention also relates to the synthesis of these compounds and to pharmaceutical compositions which contain them.

Abstract: The present invention provides a programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof. In an embodiment, the programmable modular circuit comprises a plurality of serial-to-parallel interface registers coupled together by a data line, a clock line, and an enable line. Each of the plurality of serial-to-parallel interface registers is coupled to a module of the system-on-a-chip. The data line and the clock line are used to serially clock data into the plurality of serial-to-parallel interface registers. Applying a first logical value to the enable line provides the data serially clocked into the plurality of serial-to-parallel interface registers to modules of the system-on-a-chip. Applying a second logical value to the enable line provides default values to modules of the system-on-a-chip.

Abstract: The present invention provides a programmable modular circuit for testing and controlling a system-on-a-chip integrated circuit, and applications thereof. In an embodiment, the programmable modular circuit comprises a plurality of serial-to-parallel interface registers coupled together by a data line, a clock line, and an enable line. Each of the plurality of serial-to-parallel interface registers is coupled to a module of the system-on-a-chip. The data line and the clock line are used to serially clock data into the plurality of serial-to-parallel interface registers. Applying a first logical value to the enable line provides the data serially clocked into the plurality of serial-to-parallel interface registers to modules of the system-on-a-chip. Applying a second logical value to the enable line provides default values to modules of the system-on-a-chip.