Patents by Inventor Antonius Martinus Jacobus Daanen
Antonius Martinus Jacobus Daanen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11520363Abstract: A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.Type: GrantFiled: September 22, 2020Date of Patent: December 6, 2022Assignee: NXP B.V.Inventors: Antonius Martinus Jacobus Daanen, Klaas-Jan de Langen, Sybren Matthias Bouwhuis
-
Patent number: 11456745Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.Type: GrantFiled: September 22, 2020Date of Patent: September 27, 2022Assignee: NXP B.V.Inventors: Klaas-Jan de Langen, Antonius Martinus Jacobus Daanen, Frederik van den Ende
-
Publication number: 20210126638Abstract: An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.Type: ApplicationFiled: September 22, 2020Publication date: April 29, 2021Inventors: Klaas-Jan de Langen, Antonius Martinus Jacobus Daanen, Frederik van den Ende
-
Publication number: 20210124381Abstract: A system comprising: a LDO regulator configured to receive a supply voltage and provide an output voltage based on a function of the supply voltage, the LDO regulator switchable between at least a first and second mode, wherein the first and second modes each define the output voltage provided to the output terminal based on different functions of the supply voltage; and a digital logic controller configured to select the mode of the LDO regulator by control signalling to the LDO regulator, the digital logic controller configured to receive power for the provision of the control signalling from the LDO regulator; wherein the LDO regulator comprises LDO start-up circuitry configured to cause the LDO regulator, during start-up, to default to a predetermined one of the first and second mode and the LDO start-up circuitry further configured to prevent the digital logic controller from controlling the mode of the LDO regulator.Type: ApplicationFiled: September 22, 2020Publication date: April 29, 2021Inventors: Antonius Martinus Jacobus Daanen, Klaas-Jan de Langen, Sybren Matthias Bouwhuis
-
Patent number: 10712772Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.Type: GrantFiled: March 26, 2018Date of Patent: July 14, 2020Assignee: NXP B.V.Inventors: Antonius Martinus Jacobus Daanen, Guillaume Lemaitre, William Gerard Leijenaar, Michael Levi
-
Patent number: 10431317Abstract: A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.Type: GrantFiled: March 1, 2018Date of Patent: October 1, 2019Assignee: NXP B.V.Inventor: Antonius Martinus Jacobus Daanen
-
Publication number: 20190074071Abstract: A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.Type: ApplicationFiled: March 1, 2018Publication date: March 7, 2019Inventor: Antonius Martinus Jacobus Daanen
-
Publication number: 20180284836Abstract: A data-processing-circuit comprising: a clock-input-terminal configured to receive a clock-signal; a data-output-terminal configured to provide a data-output-signal; an adjustable-driver-buffer configured to: receive a data-signal; and apply a driver-strength-value to the data-signal in order to provide a data-output-signal, wherein the current level of the data-output-signal is based on the driver-strength-value; and a driver-control-module comprising: a time-alignment-module configured to: process the clock-signal and the data-output-signal in order to determine a timing-delay-signal that is representative of a time delay between: a transition in the clock-signal; and a transition in the data-output-signal; provide the driver-strength-value for the adjustable-driver-buffer based on the timing-delay-signal and a target-delay-signal, wherein the driver-strength-value is for reducing a difference between: the timing-delay-signal; and the target-delay-signal.Type: ApplicationFiled: March 26, 2018Publication date: October 4, 2018Inventors: Antonius Martinus Jacobus Daanen, Guillaume Lemaitre, William Gerard Leijenaar, Michael Levi