Abstract: A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.

Abstract: A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the read port and the write port that permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art. An address collision detector is provided such that when both read and write ports in the SRAM block access the same address simultaneously a choice between the data being read can be made between the data presently in the SRAM block or the new data being written to the SRAM block.

Abstract: A static random access memory (SRAM) having a reduced access time for reading and reduced probability of inadvertent writing operations. Switching circuits (multiplexers) that are used to connect column bit lines with reading and writing circuits of the memory are divided into separate circuits for use during read and write operations. A recovery pulse is applied only to bit lines of a column just written to by use of the driving circuits through the same column line switching circuits.

Abstract: Read-only memories are manufactured to include the associated microprocessor controlling program specified by, and proprietary to, the manufacturer's customers. The problem the manufacturer has of identifying each ROM and associated microprocessor with each customer is now overcome by including an assigned customer identification number in a separate small permanent register that may be read out into the data bus by an appropriate input signal. Stored program security is provided by including in the ROM test circuit a fusible link that may be opened by an appropriate signal to prevent all future readout of the customer's proprietary program.

Abstract: On-chip circuitry for measuring the threshold voltage and hence the data retention reliability of the floating gate transistors used in erasable programmable read-only computer memories. Upon the application of a program "verification" signal, an externally adjustable and calibrated voltage ramp is applied by the test circuit to each of the memory X-lines coupled to the gate elements of the memory transistors. The threshold voltage of a selected transistor can then be determined by increasing the voltage ramp to the point at which the transistor will read out.