Patents by Inventor Antti Iihola

Antti Iihola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116753
    Abstract: A method is provided for sealing and contacting a microelectromechanical device that includes a silicon device wafer with MEMS device structures and a cap wafer with an electrical circuit. The device wafer includes a sealing region and an interconnection region. Moreover, the cap wafer includes a corresponding sealing region and an interconnection region. Layers of eutectic metal alloy material are deposited on the sealing and the interconnection regions of the device wafer and the cap wafer. The cap wafer is bonded to the device wafer so that the interconnection region of the device wafer is aligned with the interconnection region of the cap wafer and the sealing region of the device wafer is aligned with the sealing region of the cap wafer.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 11, 2024
    Inventors: Antti IIHOLA, Jeanette LINDROOS
  • Patent number: 11792941
    Abstract: The present publication discloses a circuit-board structure, including a conductor layer on an insulating material layer, and a conductor pattern on top of the conductor foil. A component is attached to the conductor foil and the conductor pattern, the component embedded at least in part in adhesive which attaches the component to the insulating material layer. A recess is formed in the conductor foil and the insulating material layer, and contact openings are in the insulating material layer at locations of contact areas of the component. Conductor material of the conductor foil is not present outside the conductor pattern, and the conductor foil is located between the conductor pattern and the insulating material layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 17, 2023
    Assignee: IMBERATEK, LLC
    Inventors: Risto Tuominen, Antti Iihola, Petteri Palm
  • Patent number: 11716816
    Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 1, 2023
    Assignee: IMBERATEK, LLC
    Inventors: Antti Iihola, Timo Jokela
  • Publication number: 20210392752
    Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Risto Tuominen, Antti Iihola, Petteri Palm
  • Publication number: 20210329788
    Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Antti Iihola, Timo Jokela
  • Patent number: 11134572
    Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 28, 2021
    Assignee: IMBERATEK, LLC
    Inventors: Risto Tuominen, Antti Iihola, Petteri Palm
  • Patent number: 10798823
    Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 6, 2020
    Assignee: IMBERATEK, LLC
    Inventors: Antti Iihola, Timo Jokela
  • Publication number: 20200283292
    Abstract: A microelectromechanical structure including a first wafer structure attached by bonding to a second wafer structure. The first wafer structure includes a build part of silicon wafer material, a through via, and an isolation structure separating the through via from the build part. The through via extends between a first electrical contact and a second electrical contact through the first wafer structure in a first direction. The first electrical contact of the first wafer structure is accessible externally and the second electrical contact of the first wafer structure connects to an internal electrical contact on the second wafer structure. In the first direction, the extent of the isolation structure includes a hollow section and a via fill section where the isolation structure is filled with solid electrically insulating material. enables considerable increase of gap height in MEMS structures.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 10, 2020
    Inventors: Altti TORKKELI, Antti IIHOLA
  • Publication number: 20200187358
    Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Inventors: Antti Iihola, Timo Jokela
  • Patent number: 10231335
    Abstract: The present invention generally provides a novel method for manufacturing an electronic module with crossed conducting lines and a novel electronic module with crossed conducting lines. In particular, an aspect of the present invention is to provide a thin, single layer electronic module. It is also an object of the present invention to provide an electronic module with an embedded jumper element having reliable high quality connections and contacts. To achieve at least some of the aspects of the present invention, an embedded pre-fabricated jumper module is placed inside a printed circuit board which allows the crossing of conducting lines within the module without manufacturing additional layers over the whole PCB board. The resultant PCB will have improved contacts and will not have surface deformation.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 12, 2019
    Assignee: GE Embedded Electronics Oy
    Inventors: Petteri Palm, Tuomas Waris, Antti Iihola
  • Patent number: 10085347
    Abstract: Method for the manufacture of a circuit board containing a component and circuit board containing a component. The invention is based on first manufacturing (101-102 or 101-103) an intermediate product, which contains the insulator layer of the circuit board and the components, which are set in place inside the insulator layer, in such a way that the contact elements of the components face the surface of the intermediate product. After this, the intermediate product is transferred to the circuit-board manufacturing line, on which a suitable number of conducting-pattern layers and, if necessary, insulator layers are manufactured (104) on one or both sides of the intermediate product, in such a way that, when manufacturing the first conducting-pattern layer, the conductor material forms an electrical contact with the contact elements of the components. Alternatively, stages (101-105) can also be performed on a single manufacturing line.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: September 25, 2018
    Assignee: GE Embedded Electronics Oy
    Inventors: Risto Tuominen, Petteri Palm, Antti Iihola
  • Patent number: 9969615
    Abstract: A method for manufacturing a micromechanical device layer is performed on a device wafer comprising a single layer of homogenous material. The method comprises patterning a first mask on a first face of the device wafer, the first mask patterning at least lateral dimensions of comb structures and outlines of large device structures. First trenches are etched, the first trenches defining the lateral dimensions of the at least comb structures and outlines of large device structures in a single deep etching process. Recession etching may be used on one or two faces of the device wafer for creating structures at least partially recessed below the respective surfaces of the device wafer. A double mask etching process may be used on one or two faces of the device wafer for creating structures at least partially recessed to mutually varying depths from the respective face of the device wafer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 15, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Antti Iihola, Altti Torkkeli
  • Patent number: 9883587
    Abstract: Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 30, 2018
    Assignee: GE Embedded Electronics Oy
    Inventors: Petteri Palm, Risto Tuominen, Antti Iihola
  • Patent number: 9820375
    Abstract: Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 14, 2017
    Assignee: GE Embedded Electronics Oy
    Inventors: Antti Iihola, Tuomas Waris
  • Publication number: 20170271288
    Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.
    Type: Application
    Filed: June 2, 2017
    Publication date: September 21, 2017
    Inventors: Antti Iihola, Risto Tuominen
  • Patent number: 9764942
    Abstract: The present invention relates to a micromechanical device comprising a multi-layer micromechanical structure including only homogenous silicon material. The device layer comprises at least a rotor and at least two stators. At least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a first surface of the device layer and at least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a second surface of the device layer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 19, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Antti Iihola, Altti Torkkeli, Ville-Pekka Rytkönen, Matti Liukku
  • Patent number: 9691724
    Abstract: Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: June 27, 2017
    Assignee: GE Embedded Electronics Oy
    Inventors: Antti Iihola, Risto Tuominen
  • Patent number: 9674948
    Abstract: Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 6, 2017
    Assignee: GE Embedded Electronics Oy
    Inventors: Antti Iihola, Tuomas Waris
  • Publication number: 20170127508
    Abstract: Rigid-flex-type circuit-board structure and manufacturing method, in which a flexible membrane and a sacrificial-material piece are attached to an insulator membrane in the location of the flexible zone. An insulator layer, which encloses within itself a sacrificial-material piece is manufactured on the surface of the conductor membrane. The flexible zone is formed in such a way that an opening is made in the insulator layer, through which the sacrificial-material piece is removed. The flexible zone comprises at least part of the flexible membrane as well as conductors, which are manufactured by patterning the insulator membrane at a suitable stage in the method.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: Antti Iihola, Tuomas Waris
  • Patent number: 9622354
    Abstract: A method for manufacturing a circuit-board structure wherein a conductor foil is provided on an insulating material layer, a resist layer is spread on the conductor foil and a recess formed in the conductor foil and insulating material layer. The resist layer is patterned to form a conductor-pattern having openings wherein conductor patterns may be grown. A component is attached to the conductor foil and conductor pattern and conductor material is removed which does not form part of a conductor pattern.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: April 11, 2017
    Assignee: GE Embedded Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola, Petteri Palm