Abstract: Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element, wherein a loop number is incremented with each program-verify iteration includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when the loop number is less than a loop number threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the the loop number is greater than or equal to the loop number threshold corresponding to the target data state that the storage element is being programmed to.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Abstract: A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside.

Abstract: Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when a present program-verify iteration is less than a threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the present program-verify iteration is greater than or equal to the threshold corresponding to the target data state that the storage element is being programmed to.

Abstract: A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside.

Abstract: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.

Abstract: In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.

Abstract: In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.

Abstract: Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn?2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

Abstract: Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.

Abstract: In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.

Abstract: Methods and devices for sensing non-volatile storage devices in a way that reduces read disturb are disclosed. Techniques are used to reduce read disturb on memory cells that are neighbors to selected memory cells. For example, on a NAND string, the memory cells that are next to the selected memory cell presently being read may benefit. In one embodiment, when reading memory cells on a selected word line WLn, Vread+Delta is applied to WLn+2 and WLn?2. Applying Vread+Delta to the second neighbor word line may reduce read disturb to memory cells on the neighbor word line WLn+1.

Abstract: Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

Abstract: During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.

Abstract: Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.

Abstract: During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.

Abstract: Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells'threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

Abstract: Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

Abstract: Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.