Abstract: A file system in a user space partition of virtual memory may be mounted by a computing device that runs a virtual machine which includes a set of storage disks. The file system in user space may then expose one or more virtual files associated with one or more storage disks that correspond to one or more loop devices configured to map files of the virtual machine to the one or more virtual files. The computing device may then receive a request to read a data block stored at the virtual machine and may identify a file and corresponding virtual file that stores the requested data block based on a set of metadata provided by the loop devices. The computing device may then determine the location of the data block stored at the virtual machine, and may read the data block from the determined location.

Abstract: A file system in a user space partition of virtual memory may be mounted by a computing device that runs a virtual machine which includes a set of storage disks. The file system in user space may then expose one or more virtual files associated with one or more storage disks that correspond to one or more loop devices configured to map files of the virtual machine to the one or more virtual files. The computing device may then receive a request to read a data block stored at the virtual machine and may identify a file and corresponding virtual file that stores the requested data block based on a set of metadata provided by the loop devices. The computing device may then determine the location of the data block stored at the virtual machine, and may read the data block from the determined location.

Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Abstract: A system and method for generating a set of ordered deployment domains to verify and deploy a change in a plurality of electronic devices' variants. The method encompasses receiving, at a processing unit [102], unordered deployment domain/s. Further the method encompasses identifying, by an identification unit [104], a set of plurality of electronic devices' variants present in each deployment domain of the unordered deployment domain/s. The method thereafter encompasses identifying, by the identification unit [104], a number of electronic devices' variants in each set of plurality of electronic devices' variants. Further the method encompasses ordering, by the processing unit [102], each deployment domain of the unordered deployment domain/s in a specific order based on the identified number of electronic devices' variants in each set of plurality of electronic devices' variants, to generate the set of ordered deployment domains based on the specific order.

Abstract: A method for grouping data in a data center into one or more maintenance domains (MD) which then processed, copied and mirror hosted as one or copies of maintenance domain. Each application running in the data center is evenly distributed across the MDs. For an maintenance one or more copy of the MD is updated and changes propagated through the copies of hosted MD. Thus, successfully shutting down only one or more MD for maintenance without affecting the availability of entire data center.

Abstract: A Protocol Analyzer is provided for monitoring and debugging a high-speed communications link between a local device and a remote device. The local device may include a communications protocol block for interfacing with the remote device. The Protocol Analyzer may include an embedded logic debugging circuit on the local device, where the logic debugging circuit is configured to capture link data based on user-defined events to create a corresponding database of signal capture in a local memory. The Protocol Analyzer is configured to import the database from memory and to decode the link data to display on a user interface that organizes key link sequencing events along with their timestamps to help the user more accurately and quickly debug any link bring-up issues.

Abstract: This invention makes capacity fluid among multiple kubernetes clusters maintained by an organization by introducing a system and method named capacity middleware to shrink and grow clusters based on their resource requirements. Capacity Middleware, run on the Management Cluster alongside an API controlling Clusters and assigns annotations related to priority on objects of Cluster resource, annotation for no preemption Quota to objects of MachineDeployment specifying the number of resources for each cluster and annotation of valid capacity (capacityValidated) by default set to false on objects of Machine resource which is used by the Capacity Middleware as a signal to respond to these objects. The capacity middleware iteratively checks and frees or assigns resources based needs of different clusters based on difference between required capacity and available capacity. A difference of negative suggests need for preempting resource whereas a difference in positive number suggest additionally required resources.

Abstract: An integrated circuit has a transceiver circuit and a memory circuit. The transceiver circuit includes stage circuits that each perform at least one function specified by a data transmission protocol. The transceiver circuit is coupled to receive packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a timestamp in response to receiving each of the packets of timing test patterns. Each of the stage circuits in the transceiver circuit generates a trigger indicating receipt of a predefined reference point in each of the packets of timing test patterns. The memory circuit stores each of the timestamps generated by the stage circuits in response to a respective one of the triggers and outputs the timestamps for analysis.

Abstract: A Protocol Analyzer is provided for monitoring and debugging a high-speed communications link between a local device and a remote device. The local device may include a communications protocol block for interfacing with the remote device. The Protocol Analyzer may include an embedded logic debugging circuit on the local device, where the logic debugging circuit is configured to capture link data based on user-defined events to create a corresponding database of signal capture in a local memory. The Protocol Analyzer is configured to import the database from memory and to decode the link data to display on a user interface that organizes key link sequencing events along with their timestamps to help the user more accurately and quickly debug any link bring-up issues.