Abstract: An integrated circuit and mirror device. The device includes a first substrate comprising a plurality of electrode groups, wherein each of the groups comprises a plurality of electrodes. A mirror array is formed on a second substrate. Each of the mirrors on the array has a mirror surface being able to pivot about a point (e.g., fixed point, region) in space. Each of the mirrors has a backside surface operably coupled to one of the electrode groups. A bonding layer mechanically couples the first substrate to the second substrate, whereupon the backside surface of each mirror faces one of the electrode groups. The device also has a drive circuitry coupled to each electrode groups. The drive circuitry is configured to apply a voltage to any one of the electrodes in each of the electrode groups. The drive circuitry is disposed in the first substrate and being adapted to pivot each of the mirror faces about the point in space.

Abstract: An integrated circuit and mirror device and method. The device has a first substrate comprising a plurality of electrode groups, which comprise a plurality of electrodes. The device also has a mirror array formed on a second substrate. Each of the mirrors on the array has a mirror surface being able to pivot about a point in space. Each of the mirrors has a backside surface operably coupled to one of the electrode groups. The device has a capacitance spacer layer disposed between each of the electrode groups and its respective mirror. The mirror is one from the mirror array. A drive circuitry is coupled to each electrode groups. The drive circuitry is configured to apply a drive voltage to any one of the electrodes in each of the electrode groups. The drive circuitry is also disposed in the first substrate and is adapted to pivot each of the mirror faces about the point in space.

Abstract: Architecture, circuitry, and methods are provided for testing one or more integrated circuits which may be arranged upon a printed circuit board. The integrated circuits include sequential and combinatorial logic used by the integrated circuit during normal functioning thereof. Testing of that logic can occur by sending test vectors in parallel or serial form to input pins of the integrated circuit. The test results can either be read as a serial data stream or as a parallel-delivered data stream. If the test information and results occur in parallel fashion, than automated test equipment can be used which do not require compliance with having a single serial fed test vector input and test result output, normally found in a TAP application. A parallel/serial multiplexer is used to select whether the integrated circuit receives parallel or serial test vectors, and another parallel/serial multiplexer is used to select whether the test results are to be delivered in parallel or serial fashion.

Abstract: A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit.