Patents by Inventor Anurag Ramesh Tiwari

Anurag Ramesh Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for on-chip duty cycle measurement
    Patent number: 8212547
    Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: July 3, 2012
    Assignee: STMicroelectronics International N.V.
    Inventors: Anurag Ramesh Tiwari, Kallol Chatterjee
  • SYSTEM AND METHOD FOR ON-CHIP DUTY CYCLE MEASUREMENT
    Publication number: 20100019757
    Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.
    Type: Application
    Filed: July 22, 2009
    Publication date: January 28, 2010
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Anurag Ramesh Tiwari, Kallol Chatterjee