Abstract: Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Abstract: Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL.

Abstract: Disclosed is a device and method for providing a bounded bias voltage with improved Process Voltage Temperature (PVT) adjustment. An embodiment may include a bias_n generation circuit that adjusts a bias_n voltage for PVT as a function of two bias_n NMOS transistors/diodes and a bias_p generation circuit that adjusts a bias_p voltage for PVT as a function of two bias_p PMOS transistors/diodes. An embodiment may further include a PVT adjusted bounded bias voltage circuit comprised of a NMOS transistor with the bias_n voltage at the gate and a PMOS transistor with the bias_p voltage at the gate such that a common connection between the NMOS and PMOS transistors generates a bounded bias voltage adjusted for PVT as a function of two body biased voltages (bias_n/bias_p). The bounded bias voltage may be used to provide a low supply voltage to a low voltage device using an available high voltage supply.

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract: Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source.

Abstract: Circuits and systems including a startup circuit coupled to a reference source for providing startup current to the reference source wherein no transistor of the startup circuit experiences a stress condition and wherein the startup circuit consumes no static current following stabilized, steady-state operation of the reference source.