Patents by Inventor Anvitha Shampur

Anvitha Shampur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11610839
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 21, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Tung-Hsing Lee, Teng-Yin Lin, Frank W. Mont, Edward J. Gordon, Asmaa Elkadi, Alexander Martin, Won Suk Lee, Anvitha Shampur
  • Patent number: 11195947
    Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 7, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jagar Singh, Luigi Pantisano, Anvitha Shampur, Frank Scott Johnson, Srikanth Balaji Samavedam
  • Patent number: 11011303
    Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 18, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Tung-Hsing Lee, Roderick A Augur, Siva R K Dangeti, Alexander L. Martin, Anvitha Shampur
  • Publication number: 20210126126
    Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Inventors: Jagar Singh, Luigi Pantisano, Anvitha Shampur, Frank Scott Johnson, Srikanth Balaji Samavedam
  • Publication number: 20210125922
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Tung-Hsing LEE, Teng-Yin LIN, Frank W. MONT, Edward J. GORDON, Asmaa ELKADI, Alexander MARTIN, Won Suk LEE, Anvitha SHAMPUR
  • Publication number: 20200066438
    Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Tung-Hsing Lee, Roderick A Augur, Siva R K Dangeti, Alexander L. Martin, Anvitha Shampur