Patents by Inventor Anwar Ali
Anwar Ali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240096745Abstract: A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventors: Mayank Mayukh, Anwar Ali, Jayanthi Pallinti, Shrikara Prabhu Tendel, Gregory Dix
-
Publication number: 20230245973Abstract: An electrical device for transporting electrical signals, wherein the electrical device comprises a plurality of signal wires each configured for transporting electrical signals, and a plurality of shield wires being staggered with respect to each other and each being configured for shielding signal wires with respect to each other, wherein each shield wire is arranged between a respective pair of signal wires and extends only along a subsection of each signal wire of the respective pair.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Mohamed Anwar Ali, James Robert Church, Sudersan Sampath, Roger A. Fratti
-
Patent number: 11538790Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.Type: GrantFiled: September 30, 2021Date of Patent: December 27, 2022Assignee: BROADCOM INTERNATIONAL PTE. LTD.Inventors: Mohamed Anwar Ali, Thinh Quang Tran, Tauman T. Lau
-
Publication number: 20220302080Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.Type: ApplicationFiled: September 30, 2021Publication date: September 22, 2022Inventors: Mohamed Anwar Ali, Thinh Quang Tran, Tauman T. Lau
-
Patent number: 11246833Abstract: A method of producing an extruded, powdered/granulated composition comprising an active pharmaceutical ingredient (API), by the steps of providing an API and a porous inorganic excipient, and processing them by an extrusion process to directly produce an extruded, powdered/granulated composition wherein the API is at least partially absorbed within the pores of the inorganic excipient. In preferred embodiments, the API is melted, or solubilised in a solubilizer.Type: GrantFiled: February 9, 2016Date of Patent: February 15, 2022Assignees: Cubic Pharmaceuticals Ltd., Delta Pharmaceuticals Ltd.Inventors: Dennis Douroumis, Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
-
Patent number: 10881616Abstract: The invention relates to a process of preparing a salt of an active pharmaceutical ingredient, the process comprising providing a blend of an active pharmaceutical ingredient and a salt forming substance, mixing the blend, optionally in the presence of added water, to react the active pharmaceutical ingredient with the salt forming substance to provide the salt of the active pharmaceutical ingredient; wherein when the active pharmaceutical ingredient is acidic, the salt forming substance is a base and the pKa difference between the acidic active pharmaceutical ingredient and the base is greater than 1, typically greater than 2 or preferably greater than 3; or when the active pharmaceutical ingredient is basic, the salt forming substance is an acid and the pKa difference between the basic active pharmaceutical ingredient and the acid is greater than 1, typically greater than 2 or preferably greater than 3.Type: GrantFiled: January 16, 2017Date of Patent: January 5, 2021Assignees: Cubic Pharmaceuticals Ltd., University of GreenwichInventors: Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
-
Publication number: 20190022010Abstract: The invention relates to a process of preparing a salt of an active pharmaceutical ingredient, the process comprising providing a blend of an active pharmaceutical ingredient and a salt forming substance, mixing the blend, optionally in the presence of added water, to react the active pharmaceutical ingredient with the salt forming substance to provide the salt of the active pharmaceutical ingredient; wherein when the active pharmaceutical ingredient is acidic, the salt forming substance is a base and the pKa difference between the acidic active pharmaceutical ingredient and the base is greater than 1, typically greater than 2 or preferably greater than 3; or when the active pharmaceutical ingredient is basic, the salt forming substance is an acid and the pKa difference between the basic active pharmaceutical ingredient and the acid is greater than 1, typically greater than 2 or preferably greater than 3,Type: ApplicationFiled: January 16, 2017Publication date: January 24, 2019Inventors: Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
-
Publication number: 20180021263Abstract: The present invention relates to a method of producing a direct compression tablet composition comprising the step of processing ibuprofen, a hydrophilic polymer, and an inorganic excipient by an extrusion process to produce an extruded composition in which the ibuprofen forms a solid dispersion/solution within the hydrophilic polymer. The invention is particularly useful in preparing oral dissolvable tablets. Also provided are composition comprising an inorganic excipient and ibuprofen within a hydrophilic polymer.Type: ApplicationFiled: February 9, 2016Publication date: January 25, 2018Inventors: Dennis Douroumis, Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
-
Publication number: 20180015040Abstract: A method of producing an extruded, powdered/granulated composition comprising an active pharmaceutical ingredient (API), by the steps of providing an API and a porous inorganic excipient, and processing them by an extrusion process to directly produce an extruded, powdered/granulated composition wherein the API is at least partially absorbed within the pores of the inorganic excipient. In preferred embodiments, the API is melted, or solubilised in a solubilizer.Type: ApplicationFiled: February 9, 2016Publication date: January 18, 2018Inventors: Dennis Douroumis, Mohammed Maniruzzaman, Saumil Kiritkumar Bhatt, Anwar Ali, Arun Jangra
-
Publication number: 20140312475Abstract: A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each electrical intra-die path can optionally include one or more respective buffer circuits configured to reduce degradation of the various signals that are being shared by the reused dies. In some embodiments, multiple reused dies can be arranged in a linear or two-dimensional array on an interposer or on the package substrate and packaged together with one or more non-reused dies in a single integrated-circuit package.Type: ApplicationFiled: April 26, 2013Publication date: October 23, 2014Applicant: LSI CORPORATIONInventors: Anwar Ali, Gokulnath S. Sulur, Tauman T. Lau
-
Publication number: 20130154109Abstract: The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: LSI CorporationInventors: Ramnath Venkatraman, John W. Osenbach, Anwar Ali, Donald E. Hawk, Robert J. Madge
-
Patent number: 8350375Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.Type: GrantFiled: May 15, 2008Date of Patent: January 8, 2013Assignee: LSI Logic CorporationInventors: Anwar Ali, Kalyan Doddapaneni, Wilson Leung
-
Patent number: 8151237Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.Type: GrantFiled: August 22, 2008Date of Patent: April 3, 2012Assignee: LSI CorporationInventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
-
Patent number: 8115321Abstract: An integrated circuit includes a number of probe pads arranged in a staggered manner in a core region of the integrated circuit and a number of bond pads in an Input/Output (I/O) region surrounding the core region. The core region includes logic circuitry therein, and the I/O region is configured to enable the core region to communicate with one or more external circuit(s) through the number of bond pads. The integrated circuit also includes a die metal interconnect separating a bond pad area in the I/O region from a probe pad area in the core region. A dimension of the die metal interconnect and/or a position of the die metal interconnect between the probe pad area and the bond pad area is variable.Type: GrantFiled: April 30, 2009Date of Patent: February 14, 2012Assignee: LSI CorporationInventors: Anwar Ali, Kalyan Doddapaneni, Gokulnath Sulur, Wilson Leung, Tauman T Lau
-
Patent number: 7863716Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.Type: GrantFiled: July 23, 2009Date of Patent: January 4, 2011Assignee: LSI CorporationInventors: Anwar Ali, Tauman T Lau, Kalyan Doddapaneni
-
Publication number: 20100276816Abstract: Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Inventors: ANWAR ALI, Kalyan Doddapaneni, Gokulnath Sulur, Wilson Leung, Tauman T. Lau
-
Patent number: 7737564Abstract: A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.Type: GrantFiled: January 19, 2006Date of Patent: June 15, 2010Assignee: LSI CorporationInventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni
-
Publication number: 20090321897Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.Type: ApplicationFiled: July 23, 2009Publication date: December 31, 2009Inventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni
-
Publication number: 20090283904Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: LSI LOGIC CORPORATIONInventors: Anwar Ali, Kalyan Doddapaneni, Wilson Leung
-
Patent number: 7569472Abstract: A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.Type: GrantFiled: October 31, 2006Date of Patent: August 4, 2009Assignee: LSI CorporationInventors: Anwar Ali, Tauman T Lau, Kalyan Doddapaneni