Abstract: Examples disclosed herein relate to log events for root cause error diagnosis. A deep learning model including parameters that are trained to identify relevance of log event information to diagnose root cause errors associated with a computing device is used. In one example, log event information is received. The log event information is processed according to the deep learning model to determine, for each log event, whether to store the log event information in a buffer based on relevance of the log event information to diagnosis of root cause errors.

Abstract: Examples disclosed herein relate to a baseboard management controller (BMC) capable of execution while a computing device is powered to an auxiliary state. The BMC is to process an error log according to a deep learning model to determine one of multiple field replaceable units to deconfigure in response to the error condition. The BMC is to deconfigure the field replaceable unit. The computing device is rebooted. In response to the reboot of the computing device the BMC is to determine whether the error condition persists.

Abstract: Examples herein disclose a cache controller to receive a cache signal. A physical unclonable function (PUF) circuit is coupled to the cache controller. The PUF circuit obscures the cache signal in response to the cache signal receipt.

Abstract: Examples disclosed herein relate to log events for root cause error diagnosis. A deep learning model including parameters that are trained to identify relevance of log event information to diagnose root cause errors associated with a computing device is used. In one example, log event information is received. The log event information is processed according to the deep learning model to determine, for each log event, whether to store the log event information in a buffer based on relevance of the log event information to diagnosis of root cause errors.

Abstract: A template of instructions may be copied from a non-volatile memory (NVM) to a plurality of cache lines of an instruction cache of a processor. The instructions of the templates copied to the instruction cache may be executed. The templates may include a conditional branch instruction to determine if to proceed to a next template of the plurality of copied templates.

Abstract: Examples disclosed herein relate to a baseboard management controller (BMC) capable of execution while a computing device is powered to an auxiliary state. The BMC is to process an error log according to a deep learning model to determine one of multiple field replaceable units to deconfigure in response to the error condition. The BMC is to deconfigure the field replaceable unit. The computing device is rebooted. In response to the reboot of the computing device the BMC is to determine whether the error condition persists.

Abstract: Examples herein disclose a cache controller to receive a cache signal. A physical unclonable function (PUF) circuit is coupled to the cache controller. The PUF circuit obscures the cache signal in response to the cache signal receipt.

Abstract: A first threshold number of cache lines may be fetched to populate each of the ways of a first cache set of a higher level cache and each of the ways of a first cache set of a lower level cache. A second threshold number of cache lines may be fetched to map to the first cache set of the higher level cache and a second cache set of the lower level cache. The first threshold number of cache lines may be accessed from the second from the first cache set of the lower level cache.

Abstract: Embodiments herein relate to assigning processors to a memory mapped configuration. The processors having access to different buses of a Peripheral Component Interconnect (PCI) segment are quiesced. The quiesced processors are assigned a memory mapped configuration.

Abstract: A template of instructions may be copied from a non-volatile memory (NVM) to a plurality of cache lines of an instruction cache of a processor. The instructions of the templates copied to the instruction cache may be executed. The templates may include a conditional branch instruction to determine if to proceed to a next template of the plurality of copied templates.

Abstract: A first threshold number of cache lines may be fetched to populate each of the ways of a first cache set of a higher level cache and each of the ways of a first cache set of a lower level cache. A second threshold number of cache lines may be fetched to map to the first cache set of the higher level cache and a second cache set of the lower level cache. The first threshold number of cache lines may be accessed from the second from the first cache set of the lower level cache.

Abstract: Techniques for determining the voltage to be supplied to a core of a central processing unit are provided. A core of a central processing unit is monitored for errors. The voltage to be supplied to the core is determined based on the monitored errors. The voltage supplied to the core is altered based on the determined voltage.

Abstract: Embodiments herein relate to assigning processors to a memory mapped configuration. The processors having access to different buses of a Peripheral Component Interconnect (PCI) segment are quiesced. The quiesced processors are assigned a memory mapped configuration.

Abstract: A method and system for sharing platform data are described. The method for sharing platform data includes during a boot sequence of system firmware, accessing a first data structure tag associated with a resource accessible by the operating system. Also during the boot sequence of the system firmware, the method includes determining a memory address corresponding to platform specific data associated with the resource. During a boot time sequence of the system firmware, run time code is parsed. The method includes accessing a second tag that is visible to the operating system and associating it with the location of the platform specific data. This allows for the platform specific data to be consumed by an operating system during runtime in accordance with the industry common interfaces defined in ACPI.

Abstract: Systems and methods are provided for substantially mitigating leakage current. One embodiment includes an integrated circuit (IC). The IC comprises a monitoring circuit configured to control switching of one of a first voltage source and a second voltage source to an output. The IC also comprises a leakage current protection circuit configured to substantially mitigate leakage current flow between the first voltage source and the second voltage source due to an undershoot condition caused by the switching between the first and second voltage sources to the output.

Abstract: Systems and methods are provided for substantially mitigating leakage current. One embodiment includes an integrated circuit (IC). The IC comprises a monitoring circuit configured to control switching of one of a first voltage source and a second voltage source to an output. The IC also comprises a leakage current protection circuit configured to substantially mitigate leakage current flow between the first voltage source and the second voltage source due to an undershoot condition caused by the switching between the first and second voltage sources to the output.