Abstract: The absolute difference calculation circuits 101 through 10N each consisting of a subtractor which calculates the difference of two numbers each consisting of i bits and a bit inversion selector circuit which-provides the result of subtraction as it is when no borrow output is produced by the subtractor, and inverts every bit of the result of subtraction when there is a borrow output, to obtain 1's complement of the absolute value of difference. The multiple input adder 2 receives the borrow as input to the least significant bit thereof and adds the result of each absolute difference calculation circuit. Because the adding operations to obtain 2's complement in the absolute difference calculation circuit are carried out together in the multiple input adder that follows, number of adders required to calculate the absolute value of difference can be greatly reduced and the amount of entire circuitry can be greatly reduced.

Abstract: In a DCT (discrete cosine transformation)/inverse DCT arithmetic unit, data of an inputted image are inputted to a first one-dimensional N-th order DCT/inverse DCT arithmetic device using a first algorithm B. The first one-dimensional N-th order DCT/inverse DCT arithmetic device calculates a one-dimensional N-th order inverse DCT. Calculated results of the first one-dimensional N-th order DCT/inverse DCT arithmetic device are stored to a memory for intermediate results as intermediate results of the N-th order inverse DCT in M-dimensions. Similarly, a second one-dimensional N-th order DCT/inverse DCT arithmetic device calculates a one-dimensional N-th order inverse DCT using a second algorithm A, with stored data of the memory for intermediate results as an input. Calculated results of the second one-dimensional N-th order DCT/inverse DCT arithmetic device are outputted to the memory for intermediate results.

Abstract: An apparatus for detecting a motion of an image includes a first unit for calculating first partial accumulates of one block, a second unit for calculating second partial accumulates about candidate value of first partial accumulates selected in order from the smallest value and for storing total accumulates which are sums with the first and second partial accumulates, a unit for selecting a minimum total accumulate from the total accumulates stored in the second unit and for outputting the minimum total accumulate together with a location coordinate corresponding to the minimum total accumulate.

Abstract: A image processing apparatus for coloring an original image includes a unit for inputting an original image to be painted and a color image, a unit for dividing the original image input by the inputting unit into a plurality of areas corresponding to the original image and for generating area information data corresponding to the plurality of areas, a unit for selecting the same number of colors as the number of the plurality of areas based on data of the color image input by the inputting unit, and a unit for allocating the colors selected by the selecting unit to the plurality of divided areas based on the area information data.

Abstract: An apparatus for performing an inverse discrete cosine transform, which reduces the number of operation times of the inverse discrete cosine transform including a row and column priority determining unit 10 for determining a priority direction of an operation at a time when a two-dimensional inverse discrete cosine transform is replaced with at least one one-dimensional inverse discrete cosine transform, one-dimensional inverse DCT operating units 11, 13 connected to the row and column priority determining unit 10 for detecting zero elements and for performing a multiply-addition according to a result of the detection, and a random access memory 12, connected to the one-dimensional inverse DCT operating units 11, 13 for storing a result of the multiply-addition performed by the one-dimensional inverse DCT operating unit 11.

Abstract: A memory cell circuit for a CMOS static RAM is provided, which includes a latch portion for holding logic high or logic low data depending on the potential of a single bit line, and a transfer gate having a first terminal connected to the latch portion and a second terminal connected to the single bit line, the transfer gate electrically connecting or disconnecting the first and second terminals in response to a selection signal, wherein the transfer gate includes a first transistor and a second transistor connected in parallel between the first and second terminals, both of the first and second transistors being activated at a data write operation, while one of the first and second transistors being activated at a data read operation.