Patents by Inventor Aparna Iyer
Aparna Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11974338Abstract: In some implementations a system can be configured to reduce the burden of pairing user devices with playback devices. For example, all users (or user devices) who commonly operate within a particular environment (e.g., a home) can be configured as authorized users of playback devices within the particular environment. When one of the authorized users pairs a user device with a playback device, all of the user devices for all authorized users can be automatically paired with the playback device as a result of the single pairing. Thus, only a single authorized user is burdened with the pairing process in order to pair all authorized users with the playback device.Type: GrantFiled: March 25, 2021Date of Patent: April 30, 2024Assignee: Apple Inc.Inventors: Deepak Iyer, Thomas Alsina, Edward T. Schmidt, Elena Leyfman, David P. Saracino, Astrid Yi, Adam A. Sonnanstine, Jonathan A. Bennett, Gregory R. Chapman, Aparna S. Akella, Shreyas Nandagudi Sreesha
-
Patent number: 11195756Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.Type: GrantFiled: September 19, 2014Date of Patent: December 7, 2021Assignee: Applied Materials, Inc.Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Aparna Iyer, Alan Hiroshi Ouye
-
Publication number: 20200258780Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.Type: ApplicationFiled: April 30, 2020Publication date: August 13, 2020Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Brad Eaton, Aparna Iyer
-
Patent number: 10692765Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.Type: GrantFiled: November 7, 2014Date of Patent: June 23, 2020Assignee: Applied Materials, Inc.Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Brad Eaton, Aparna Iyer
-
Patent number: 9343366Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.Type: GrantFiled: November 17, 2014Date of Patent: May 17, 2016Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
-
Publication number: 20160133519Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a plasma etch apparatus includes a plasma etch chamber. The plasma etch chamber includes a plasma source disposed in an upper region of the plasma etch chamber, a cathode assembly disposed below the plasma source, and a support pedestal for supporting a substrate carrier below the plasma source. The plasma etch apparatus also includes a transfer chamber coupled to the plasma etch chamber. The transfer chamber includes a transfer arm for supporting a substantial portion of a dicing tape of the substrate carrier, the transfer arm configured to transfer a sample from the support pedestal following an etch singulation process.Type: ApplicationFiled: November 7, 2014Publication date: May 12, 2016Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Brad Eaton, Aparna Iyer
-
Patent number: 9299614Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer.Type: GrantFiled: November 11, 2014Date of Patent: March 29, 2016Assignee: Applied Materials, Inc.Inventors: James M. Holden, Brad Eaton, Aparna Iyer, Ajay Kumar
-
Publication number: 20160086852Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.Type: ApplicationFiled: September 19, 2014Publication date: March 24, 2016Inventors: James M. Holden, Alexander N. Lerner, Ajay Kumar, Aparna Iyer, Alan Hiroshi Ouye
-
Patent number: 9275902Abstract: Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.Type: GrantFiled: March 26, 2014Date of Patent: March 1, 2016Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
-
Patent number: 9236305Abstract: Laser and plasma etch wafer dicing where a mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The semiconductor wafer is coupled to a film frame by an adhesive film. The mask is patterned by laser scribing to provide a patterned mask with gaps. The laser scribing exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask while the film frame is maintained at an acceptably low temperature with a chamber shield ring configured to sit beyond the wafer edge and cover the frame. The shield ring may be raised and lowered, for example, on lifter pins to facilitate transfer of the wafer on frame.Type: GrantFiled: January 17, 2014Date of Patent: January 12, 2016Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Saravjeet Singh, Jivko Dinev, Aparna Iyer, Brad Eaton, Ajay Kumar
-
Patent number: 9177864Abstract: Methods of using a hybrid mask composed of a first water soluble film layer and a second water-soluble layer for wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a hybrid mask above the semiconductor wafer. The hybrid mask is composed of a first water-soluble layer disposed on the integrated circuits, and a second water-soluble layer disposed on the first water-soluble layer. The method also involves patterning the hybrid mask with a laser scribing process to provide a patterned hybrid mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also involves etching the semiconductor wafer through the gaps in the patterned hybrid mask to singulate the integrated circuits.Type: GrantFiled: September 5, 2014Date of Patent: November 3, 2015Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Todd Egan, Madhava Rao Yalamanchili, Ajay Kumar
-
Publication number: 20150303111Abstract: Approaches for hybrid laser scribe and plasma etch dicing process for a wafer having backside solder bumps are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof and corresponding arrays of metal bumps on a backside thereof involves applying a dicing tape to the backside of the semiconductor wafer, the dicing tape covering the arrays of metal bumps. The method also involves, subsequently, forming a mask on the front side of the semiconductor wafer, the mask covering the integrated circuits. The method also involves forming scribe lines on the front side of the semiconductor wafer with a laser scribing process, the scribe lines formed in the mask and between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the scribe lines to singulate the integrated circuits, the mask protecting the integrated circuits during the plasma etching.Type: ApplicationFiled: November 17, 2014Publication date: October 22, 2015Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
-
Publication number: 20150279739Abstract: Approaches for front side laser scribe plus backside bump formation and laser scribe and plasma etch dicing process are described. For example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves forming first scribe lines on the front side, between the integrated circuits, with a first laser scribing process. The method also involves forming arrays of metal bumps on a backside of the semiconductor wafer, each array corresponding to one of the integrated circuits. The method also involves forming second scribe lines on the backside, between the arrays of metal bumps, with a second laser scribing process, wherein the second scribe lines are aligned with the first scribe lines. The method also involves plasma etching the semiconductor wafer through the second scribe lines to singulate the integrated circuits.Type: ApplicationFiled: March 26, 2014Publication date: October 1, 2015Inventors: Wei-Sheng Lei, James S. Papanu, Aparna Iyer, Brad Eaton, Ajay Kumar
-
Patent number: 9105710Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.Type: GrantFiled: November 26, 2013Date of Patent: August 11, 2015Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Madhava Rao Yalamanchili, Ajay Kumar, Jungrae Park
-
Publication number: 20150162244Abstract: Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a carrier for supporting a wafer or substrate in an etch process includes a frame having a perimeter surrounding an inner opening. The carrier also includes a tape coupled to the frame and disposed below the inner opening of the frame, the tape comprising an etch stop layer disposed above a support layer.Type: ApplicationFiled: November 11, 2014Publication date: June 11, 2015Inventors: James M. Holden, Brad Eaton, Aparna Iyer, Ajay Kumar
-
Publication number: 20150102467Abstract: Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.Type: ApplicationFiled: December 18, 2014Publication date: April 16, 2015Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Saravjeet Singh, Todd Egan, Ajay Kumar, Seshadri Ramaswami
-
Patent number: 8999816Abstract: Approaches for protecting a wafer during plasma etching wafer dicing processes are described. In an example, a method of dicing a semiconductor wafer with a front surface having a plurality of integrated circuits thereon involves laminating a pre-patterned mask on the front surface of the semiconductor wafer. The pre-patterned mask covers the integrated circuits and exposes streets between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the streets to singulate the integrated circuits. The pre-patterned mask protects the integrated circuits during the plasma etching.Type: GrantFiled: April 18, 2014Date of Patent: April 7, 2015Assignee: Applied Materials, Inc.Inventors: James M. Holden, Aparna Iyer, Brad Eaton, Ajay Kumar
-
Patent number: 8980726Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a mask, patterning the mask with a femtosecond laser scribing process to provide a patterned mask with gaps, and ablating through an entire thickness of a semiconductor substrate to singulate the IC. Following laser-based singulation, a plasma etch is performed to remove a layer of semiconductor sidewall damaged by the laser scribe process. In the exemplary embodiment, a femtosecond laser is utilized and a 1-3 ?m thick damage layer is removed with the plasma etch. Following the plasma etch, the mask is removed, rendering the singulated die suitable for assembly/packaging.Type: GrantFiled: January 17, 2014Date of Patent: March 17, 2015Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Aparna Iyer, Brad Eaton, Madhava Rao Yalamanchili, Ajay Kumar
-
Patent number: 8975162Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. For example, a method includes applying a protection tape to a wafer front side, the wafer having a dicing tape attached to the wafer backside. The dicing tape is removed from the wafer backside to expose a die attach film disposed between the wafer backside and the dicing tape. Alternatively, if no die attach film is initially disposed between the wafer backside and the dicing tape, a die attach film is applied to the wafer backside at this operation. A water soluble mask is applied to the wafer backside. Laser scribing is performed on the wafer backside to cut through the mask, the die attach film and the wafer, including all layers included within the front side and backside of the wafer. A plasma etch is performed to treat or clean surfaces of the wafer exposed by the laser scribing. A wafer backside cleaning is performed and a second dicing tape is applied to the wafer backside.Type: GrantFiled: December 3, 2013Date of Patent: March 10, 2015Assignee: Applied Materials, Inc.Inventors: Wei-Sheng Lei, Brad Eaton, Aparna Iyer, Saravjeet Singh, Madhava Rao Yalamanchili, Ajay Kumar
-
Publication number: 20150064878Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.Type: ApplicationFiled: November 26, 2013Publication date: March 5, 2015Applicant: APPLIED MATERIALS, INC.Inventors: Wei-Sheng LEI, Brad EATON, Aparna IYER, Madhava Rao YALAMANCHILI, Ajay KUMAR, Jungrae PARK