Abstract: A method and apparatus are provided for dynamically hiding a defect in a memory. In one embodiment, an entry occupied mapping includes a plurality of fields each corresponding to an entry of a memory, and during the initial test procedure of the memory the field corresponding to a defective entry is marked to make it perceived as occupied and thus the defective entry will not be used hereafter. In another embodiment, pseudo entries are selected from a backup register pool or backup memory. Each pseudo entry corresponds to a defective entry, and subsequent access to the defective entry is redirected to the corresponded pseudo entry.

Abstract: A method and apparatus are provided for dynamically hiding a defect in a memory. In one embodiment, an entry occupied mapping includes a plurality of fields each corresponding to an entry of a memory, and during the initial test procedure of the memory the field corresponding to a defective entry is marked to make it perceived as occupied and thus the defective entry will not be used hereafter. In another embodiment, pseudo entries are selected from a backup register pool or backup memory. Each pseudo entry corresponds to a defective entry, and subsequent access to the defective entry is redirected to the corresponded pseudo entry.

Abstract: A method and apparatus are provided for dynamically hiding a defect in a memory. In one embodiment, an entry occupied mapping includes a plurality of fields each corresponding to and entry of a memory, and during the initial test procedure of the memory the field corresponding to a defective entry is marked to make it perceived as occupied and thus the defective entry will not be used hereafter. In another embodiment, pseudo entries are selected from a backup register pool or backup memory. Each pseudo entry corresponds to a defective entry, and subsequent access to the defective entry is redirected to the corresponded pseudo entry.

Abstract: A single chip Ethernet switch integrated with physical layer entity is switched between a normal mode and a daisy chain test mode by a mode select signal. Under the daisy chain test mode, each port of the switch is connected to a passive loop-back device, other than a start transmission port and a stop receiving port. A test packet is supplied to the start transmission port and transmitted eventually from the start transmission port to the stop receiving port through each port of the switch with initialization of an address table and a packet source address learning process.

Abstract: A method and apparatus is directed for dynamically hiding a defect in a memory. In one embodiment, an entry occupied mapping includes a plurality of fields each corresponding to an entry of a memory, and during the initial test procedure of the memory the field corresponding to a defective entry is marked to make it perceived as occupied and thus the defective entry will not be used hereafter. In another embodiment, pseudo entries are selected from a backup register pool or backup memory, each pseudo entry corresponds to a defective entry, and subsequent access to the defective entry is redirected to the corresponded pseudo entry.

Abstract: The present invention discloses a method for adjusting an Inter-Frame Gap (IFG) in a desired ratio. Based on the method, the lengths of the first part and the second part of an Inter-Frame Gap are adjusted in such a way that their increased amount or decreased amount are always approximately in a specified ratio. Better configuration of an IFG can thus be maintained all the time, and larger adjustable range of an IFG can thus be achieved.

Abstract: The present invention relates to a slot control method of a multi-port network switch and a switch structure therefor. More particularly, the present invention relates to a slot control method of a shared memory structure with a fixed sequence and a dynamic slot effect. According to the present invention, a slot processor is provided in a slot controller of a network switch for controlling and sequentially allowing a plurality of transportation ports connected to the slot controller to perform data transmission in a fixed round-robin manner while a maximum allowable slot time is set. The slot controller continuously detects whether active transportation port sends an operation request signal or whether the maximum allowable slot time is exceeded. If there is no operation request signal or the allowable slot time is exceeded, data transmission of the next transportation port is allowed and performed immediately, thereby reducing the packet latency.