Abstract: A signal is sampled and the samples are divided into windows. One of at least three values is associated with a respective window based on whether the samples in the window are relatively constant, incremental or decremental, to thereby generate an approximation vector. Locations of thresholds in the approximation vector are determined, to generate a threshold position vector. Threshold values are assigned to the threshold positions in the threshold position vector. The threshold values, taken alone or in combination with a threshold position vector, may be used to characterize the signal. A training sequence may be used to adapt the functionality to individual needs.

Abstract: A signal is sampled and the samples are divided into windows. One of at least three values is associated with a respective window based on whether the samples in the window are relatively constant, incremental or decremental, to thereby generate an approximation vector. Locations of thresholds in the approximation vector are determined, to generate a threshold position vector. Threshold values are assigned to the threshold positions in the threshold position vector. The threshold values, taken alone or in combination with a threshold position vector, may be used to characterize the signal. A training sequence may be used to adapt the functionality to individual needs.

Abstract: A prefetching replicated instruction stream machine (PRISM) computer architecture which provides sustained instruction stream performance comparable to peak performance in computer systems with instruction pipelines operates by partitioning, prior to execution, a computer program to be executed into instruction segments based on entry point and branch target instructions defining the flow changes within the program; storing selected segments in a plurality of instruction decoding units (IDUs) such that all instructions that potentially could be needed when the next instruction is executed by a central processing unit (CPU) are stored in the IDUs, and such that no single IDU contains both a segment having a branch taken instruction and a segment containing a branch not taken instruction for the same branch instruction; simultaneously decoding in a predetermined order the instruction segments stored in each IDU; and selectively communicating instructions decoded by the IDUs to the CPU in response to the value o