Patents by Inventor Arash Hazeghi

Arash Hazeghi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8704537
    Abstract: The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than G?DUT, where G is the gain provided by the bridge circuit transistor and ?DUT is the AC signal applied to the device under test. Experiments on graphene devices and on carbon nanotube FETs demonstrate about 10 aF resolution (graphene) and about 13 aF resolution (carbon nanotube FET) at room temperature.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 22, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Arash Hazeghi, Joseph A. Sulpizio, David J. K. Goldhaber, H. S. Philip Wong
  • Publication number: 20140030627
    Abstract: An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 30, 2014
    Applicant: Quswami, Inc.
    Inventors: Jawahar Gidwani, Arash Hazeghi, Andrew Lam, Attila Horvath
  • Publication number: 20130076378
    Abstract: The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than G?DUT, where G is the gain provided by the bridge circuit transistor and ?DUT is the AC signal applied to the device under test. Experiments on graphene devices and on carbon nanotube FETs demonstrate about 10 aF resolution (graphene) and about 13 aF resolution (carbon nanotube FET) at room temperature.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Inventors: Arash Hazeghi, Joseph A. Sulpizio, David J.K. Goldhaber, H.S. Philip Wong
  • Publication number: 20130059134
    Abstract: A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanaostructure and metal elements is provided.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Inventors: Yang Chai, Arash Hazeghi, Kuniharu Takei, Ali Javey, H.S. Philip Wong
  • Publication number: 20130048070
    Abstract: A tunneling photovoltaic (“TPV”) device using a high-? dielectric as a tunneling layer is disclosed. The TPV includes a P-type doped silicon semiconductor substrate. Formed on its surface is an interfacial layer, between the semiconductor substrate and the high-? tunneling layer. Formed on the high-? tunneling layer is an electrode layer, or stack electrode layer, receiving charge carriers that tunnel through the tunneling layer, generating a current when the device is illuminated by light. The tunneling layer can be hafnium oxide or other suitable high-? dielectrics. A method of fabricating a high-? TPV is also disclosed. The TPV device according to the embodiments has improved internal quantum efficiency.
    Type: Application
    Filed: August 14, 2012
    Publication date: February 28, 2013
    Inventors: Arash Hazeghi, Vivek Subramanian