Abstract: A device includes a memory configured to store video data. The device also includes a video decoder coupled to the memory and to a cache. The video decoder is configured to decode an input frame of the video data to generate a first video frame and includes an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output.

Abstract: Aspects relate to an image signal processor that processes frames from different image sensors. An example device includes a memory and an image signal processor coupled to the memory. The image signal processor is configured to provide a first trigger to a first image sensor (the first image sensor being coupled to the image signal processor), receive a first frame from the first image sensor at a first time in response to the first trigger being received by the first image sensor, process the first frame, provide a second trigger to the second image sensor (the second image sensor being coupled to the image signal processor), receive a second frame from the second image sensor at a second time in response to the second trigger being received by the second image sensor (with the second time subsequent to the first time), and process the second frame.

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Abstract: Example techniques are described for image processing to selectively perform a warping operation if there is change in orientation of a display device between frames. For example, if there is change in orientation of a display device between processing a first frame and after rendering of a second frame, processing circuitry may perform a warp operation on the second frame to warp image content of the second frame based on a current orientation of the display device. If there is no change in orientation of the display device between processing a third frame and after rendering of a fourth frame, the processing circuitry may bypass the warp operation on the fourth frame to avoid warping entire image content of the fourth frame.

Abstract: Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Abstract: An image capture device that includes an adjustment circuit configured to monitor image parameters, generate updated image settings for the image capture device in response to the monitored image parameters, and transmit the updated image settings to one or more processors. The updated image settings configure the one or more processors to determine whether to transition the image capture device from a dynamic scene mode to a static scene mode based on a first image parameter included in the monitored image parameters, wherein the first image parameter is different from a second image parameter used to determine to transition the image capture device from the static scene mode to the dynamic scene mode, and to suspend generation of all or less than all of the updated image settings in response to determining to transition the image capture device from the dynamic scene mode to the static scene mode.

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract: An image capture device that includes an adjustment circuit configured to monitor image parameters, generate updated image settings for the image capture device in response to the monitored image parameters, and transmit the updated image settings to one or more processors. The updated image settings configure the one or more processors to determine whether to transition the image capture device from a dynamic scene mode to a static scene mode based on a first image parameter included in the monitored image parameters, wherein the first image parameter is different from a second image parameter used to determine to transition the image capture device from the static scene mode to the dynamic scene mode, and to suspend generation of all or less than all of the updated image settings in response to determining to transition the image capture device from the dynamic scene mode to the static scene mode.

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract: Techniques for intensity compensation in video processing are provided. In one configuration, a wireless communication device compliant with the VC1-SMPTE standard (e.g., cellular phone, etc.) comprises a processor that is configured to execute instructions operative to reconstruct reference frames from a received video bitstream. A non-intensity-compensated copy of a reference frame of the bitstream is stored in a memory of the device and used for defining the displayable images and for on-the-fly generation of a stream of intensity-compensated pixels to perform motion compensation calculations for frames of the video bitstream.

Abstract: A video stream (for example, H.264 video) includes intra-encoded portions. Decoding an intra-encoded portion utilizes the result of decoding one or more other portions (called predecessors) in the frame. Frame reconstruction involves identifying a portion that has no predecessor portions that have not been decoded and then initiating decoding of the identified portion(s). When the decoding of a portion is substantially complete, then the remaining portions to be decoded are examined to identify portions that have no predecessors that have not been decoded. By carrying out this method, multiple portions may be decoded simultaneously. Each can be decoded on a different work entity, thereby increasing the rate of decoding of the overall frame. Because deblock filtering a predecessor destroys information needed in the intra-decoding of other portions, prefiltered predecessor information is stored in a buffer for subsequent use during intra-decoding, thereby facilitating simultaneous decoding of multiple portions.

Abstract: The disclosure describes video decoding techniques that utilize parallel processor technology in order to accelerate the decoding processes of image frames. The techniques include defining batches of video blocks to be decoded in parallel with one another. According to this disclosure, a method may comprise defining a first batch of video blocks of an image frame, decoding the first batch of video blocks in a serial manner, defining a second batch of video blocks and a third batch of video blocks relative to the first batch of video blocks, and decoding the second and third batches of video blocks in parallel with one another.

Abstract: Techniques for intensity compensation in video processing are provided. In one configuration, a wireless communication device compliant with the VC1-SMPTE standard (e.g., cellular phone, etc.) comprises a processor that is configured to execute instructions operative to reconstruct reference frames from a received video bitstream. A non-intensity-compensated copy of a reference frame of the bitstream is stored in a memory of the device and used for defining the displayable images and for on-the-fly generation of a stream of intensity-compensated pixels to perform motion compensation calculations for frames of the video bitstream.

Abstract: The disclosure describes video decoding techniques that utilize parallel processor technology in order to accelerate the decoding processes of image frames. The techniques include defining batches of video blocks to be decoded in parallel with one another. According to this disclosure, a method may comprise defining a first batch of video blocks of an image frame, decoding the first batch of video blocks in a serial manner, defining a second batch of video blocks and a third batch of video blocks relative to the first batch of video blocks, and decoding the second and third batches of video blocks in parallel with one another.

Abstract: A video stream (for example, H.264 video) includes intra-encoded portions. Decoding an intra-encoded portion utilizes the result of decoding one or more other portions (called predecessors) in the frame. Frame reconstruction involves identifying a portion that has no predecessor portions that have not been decoded and then initiating decoding of the identified portion(s). When the decoding of a portion is substantially complete, then the remaining portions to be decoded are examined to identify portions that have no predecessors that have not been decoded. By carrying out this method, multiple portions may be decoded simultaneously. Each can be decoded on a different work entity, thereby increasing the rate of decoding of the overall frame. Because deblock filtering a predecessor destroys information needed in the intra-decoding of other portions, prefiltered predecessor information is stored in a buffer for subsequent use during intra-decoding, thereby facilitating simultaneous decoding of multiple portions.