Patents by Inventor Aravind Nayak

Aravind Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140014309
    Abstract: The invention relates to a heat sink and a method of fixing the same. In one embodiment this is accomplished by a method for bonding a heat sink and an electronic device together, wherein the heat sink including a base member and a heat radiating portion the method comprising milling the base member in the midst of the heat sink of a predetermined depth, cleaning the milled surface of the heat sink with an activator, filling the milled surface of the heat sink with an adhesive for bonding with the electronic device and placing the heat sink on the electronic device and applying force for a predetermined amount of time period.
    Type: Application
    Filed: August 11, 2011
    Publication date: January 16, 2014
    Applicant: TEJAS NETWORK LIMITED
    Inventor: Aravind Nayak
  • Patent number: 8018360
    Abstract: Methods and systems for mitigating latency in a data detector feedback loop are included. For example, a method for reducing latency in an error corrected data retrieval system is included. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: September 13, 2011
    Assignee: Agere Systems Inc.
    Inventor: Ratnakar Aravind Nayak
  • Publication number: 20100164764
    Abstract: Various embodiments of the present invention provide systems and methods for mitigating latency in a data detector feedback loop. For example, a method for reducing latency in an error corrected data retrieval system is disclosed. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.
    Type: Application
    Filed: May 19, 2008
    Publication date: July 1, 2010
    Inventor: Ratnakar Aravind Nayak
  • Patent number: 7529320
    Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: May 5, 2009
    Assignee: Agere Systems Inc.
    Inventors: Jason Byrne, German Feyh, Jeffrey Grundvig, Aravind Nayak, Richard Rauschmayer
  • Publication number: 20070064836
    Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Applicant: Agere Systems Inc.
    Inventors: Jason Byrne, German Feyh, Jeffrey Grundvig, Aravind Nayak, Richard Rauschmayer
  • Publication number: 20050169415
    Abstract: A timing error recovery system includes a phase locked loop that receives a continuous time input signal, samples the input signal at a sampling rate and generates a voltage control signal. A statistical estimator, such as a maximum a posteriori estimator, compares the voltage control signal with an expected error based upon a statistical model and produces an adjusted voltage control signal that drives a voltage controlled oscillator to adjust the sampling rate.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 4, 2005
    Applicant: Agere Systems Inc.
    Inventors: Aravind Nayak, German Feyh