Patents by Inventor Aravind S. Killampalli
Aravind S. Killampalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187507Abstract: An integrated circuit includes a body of semiconductor material. A source or drain region includes semiconductor material in contact with the body, where the semiconductor material of the source or drain region includes an outer region having a dopant concentration that is greater than a remaining region of the source or drain region, the outer region defining multiple contact surfaces of the source or drain region and extending into the source or drain region to a depth of at least 1 nm. A contact comprising a metal is on the multiple contact surfaces of the source or drain region. The dopant concentration of the outer region is continuous along the entire interface between the contact and the outer region, according to an example.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Prashant Majhi, Anand Murthy, Aravind S. Killampalli
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Patent number: 11532619Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.Type: GrantFiled: March 27, 2019Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Jack Kavalieros, Caleb Barrett, Jay P. Gupta, Nishant Gupta, Kaiwen Hsu, Byungki Jung, Aravind S. Killampalli, Justin Railsback, Supanee Sukrittanon, Prashant Wadhwa
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Patent number: 11189487Abstract: A high-pressure dielectric film curing apparatus, such as a high-pressure batch furnace, is controlled to an elevated cure temperature and super-atmospheric pressure for the duration of the film curing time with the cure pressure achieved at least partially with a vapor of aqueous ammonia in fluid communication with the chamber. The cure temperature may vary, for example between 175° C., and 400° C., or more. The cure pressure may also vary as limited by the saturated water vapor pressure, for example between 100 PSIA and 300 PSIA, or more. The aqueous ammonia may be injected into the chamber or vaporized upstream of the chamber. One or more carrier and/or diluent gas (vapor) may be introduced into the chamber to adjust the partial pressure of ammonia vapor, water vapor, and the diluent.Type: GrantFiled: September 30, 2016Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Jonathan E. Leonard, Aravind S. Killampalli, Chad Byers, Jay P. Gupta
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Publication number: 20210287901Abstract: A high-pressure dielectric film curing apparatus, such as a high-pressure batch furnace, is controlled to an elevated cure temperature and super-atmospheric pressure for the duration of the film curing time with the cure pressure achieved at least partially with a vapor of aqueous ammonia in fluid communication with the chamber. The cure temperature may vary, for example between 175° C., and 400° C., or more. The cure pressure may also vary as limited by the saturated water vapor pressure, for example between 100 PSIA and 300 PSIA, or more. The aqueous ammonia may be injected into the chamber or vaporized upstream of the chamber. One or more carrier and/or diluent gas (vapor) may be introduced into the chamber to adjust the partial pressure of ammonia vapor, water vapor, and the diluent.Type: ApplicationFiled: September 30, 2016Publication date: September 16, 2021Applicant: Intel CorporationInventors: Jonathan E. LEONARD, Aravind S. KILLAMPALLI, Chad BYERS, Jay P. GUPTA
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Patent number: 11094785Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.Type: GrantFiled: May 18, 2020Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Prashant Majhi, Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Aravind S. Killampalli, Mark R. Brazier, Jaya P. Gupta
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Patent number: 10811251Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.Type: GrantFiled: September 30, 2016Date of Patent: October 20, 2020Assignee: Intel CorporationInventors: Jeanne L. Luce, Ebony L. Mays, Aravind S. Killampalli, Jay P. Gupta
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Publication number: 20200312841Abstract: Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Jack KAVALIEROS, Caleb BARRETT, Jay P. GUPTA, Nishant GUPTA, Kaiwen HSU, Byungki JUNG, Aravind S. KILLAMPALLI, Justin RAILSBACK, Supanee SUKRITTANON, Prashant WADHWA
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Publication number: 20200286996Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.Type: ApplicationFiled: May 18, 2020Publication date: September 10, 2020Applicant: INTEL CORPORATIONInventors: PRASHANT MAJHI, GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, ARAVIND S. KILLAMPALLI, MARK R. BRAZIER, JAYA P. GUPTA
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Patent number: 10692974Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.Type: GrantFiled: September 18, 2015Date of Patent: June 23, 2020Assignee: INTEL CORPORATIONInventors: Prashant Majhi, Glenn A. Glass, Anand S. Murthy, Tahir Ghani, Aravind S. Killampalli, Mark R. Brazier, Jaya P. Gupta
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Patent number: 10573809Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.Type: GrantFiled: March 31, 2016Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Prashant Majhi, Ravi Pillarisetty, Uday Shah, Elijah V. Karpov, Niloy Mukherjee, Pulkit Jain, Aravind S. Killampalli, Jay P. Gupta, James S. Clarke
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Publication number: 20190181003Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.Type: ApplicationFiled: September 30, 2016Publication date: June 13, 2019Inventors: Jeanne L. LUCE, Ebony L. MAYS, Aravind S. KILLAMPALLI, Jay P. GUPTA
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Publication number: 20190036020Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.Type: ApplicationFiled: March 31, 2016Publication date: January 31, 2019Inventors: Prashant Majhi, Ravi Pillarisetty, Uday Shah, Elijah V. Karpov, Niloy Mukherjee, Pulkit Jain, Aravind S. Killampalli, Jay P. Gupta, James S. Clarke
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Publication number: 20180248004Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides.Type: ApplicationFiled: September 18, 2015Publication date: August 30, 2018Applicant: INTEL CORPORATIONInventors: PRASHANT MAJHI, GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, ARAVIND S. KILLAMPALLI, MARK R. BRAZIER, JAYA P. GUPTA
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Patent number: 9224602Abstract: Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.Type: GrantFiled: December 29, 2011Date of Patent: December 29, 2015Assignee: INTEL CORPORATIONInventors: Aravind S. Killampalli, Charles H. Wallace, Bernhard Sell
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Publication number: 20140117489Abstract: Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.Type: ApplicationFiled: December 29, 2011Publication date: May 1, 2014Inventors: Aravind S. Killampalli, Charles H. Wallace, Bernhard Sell
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Patent number: 7829150Abstract: Systems and methods for preparing inorganic-organic interfaces using organo-transition metal complexes and self-assembled monolayers as organic surfaces. In one embodiment, a silicon wafer is cleaned and reacted with stabilized pirhana etch to provide an oxide surface. The surface is reacted with the trichlorosilyl end of alkyltrichlorosilanes to prepare self assembling monomers (SAMs). The alkyltrichlorosilanes have the general formula R1-R—SiCl3, where R1 is —OH, —NH2, —COOH, —SH, COOCH3, —CN, and R is a conjugated hydrocarbon, such as (CH2)n where n is in the range of 3 to 18. The functionalized end of the SAM can optionally modified chemically as appropriate, and is then reacted with metal-bearing species such as tetrakis(dimethylamido)titanium, Ti[N(CH3)2]4, (TDMAT) to provide a titanium nitride layer.Type: GrantFiled: June 17, 2005Date of Patent: November 9, 2010Assignee: Cornell Research Foundation, Inc.Inventors: James R. Engstrom, Aravind S. Killampalli, Paul F. Ma