Patents by Inventor Archana Shetty

Archana Shetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash array built in self test engine with trace array and flash metric reporting
    Patent number: 8627158
    Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: David D. Cadigan, Thomas J. Griffin, Archana Shetty, Gary A. Tressler, Dustin J. Vanstee
  • FLASH ARRAY BUILT IN SELF TEST ENGINE WITH TRACE ARRAY AND FLASH METRIC REPORTING
    Publication number: 20130151914
    Abstract: A mechanism is provided for a flash array test engine. The flash array test engine includes a circuit. The circuit is configured to generate test workloads in a test mode for testing a flash device array, where each of the test workloads includes specific addresses, data, and command patterns to be sent to the flash device array. The circuit is configured to accelerate wear in the flash device array, via the test workloads, at an accelerated rate relative to general system workloads that are not part of the test mode. The circuit is configured to vary a range of conditions for the flash device array to determine whether each of the conditions passes or fails and to store failure data and corresponding failure data address information for the flash device array.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Cadigan, Thomas J. Griffin, Archana Shetty, Gary A. Tressler, Dustin J. Vanstee