Abstract: In a first aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having a pitch that is uniform among the plurality of wrapped channels. In a second aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having an asymmetric distribution. For example, a first distance between a first pair of adjacent wrapped channels is different than a second distance between a second pair of adjacent wrapped channels.

Abstract: Aspects of the disclosure includes a transistor-under-test (TUT) to charge/discharge a capacitor; changing an oscillation state when a capacitor voltage crosses a threshold and turning OFF the TUT; discharging the capacitor using the TUT; commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; commencing discharging the capacitor after a precharger time delay; sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF/ON the TUT; and generating a digital representation of a TUT current associated with a relaxation oscillator period of the relaxation oscillator waveform.

Abstract: A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

Abstract: A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

Abstract: A circuit for a low latency, low area, and low power flip-flop may include a pass-gate multiplexer that can selectively allow one of input or test data to enter a master cell when a clock signal is low. The master cell may include a first inverter cross-coupled to a second inverter, and may receive the input or test data and may latch and provide at an input node of the slave cell, an inverted input data or the test data, upon a transition of the clock signal to a high state. The slave cell may include a second clock pass-gate and a third inverter that is cross-coupled to a fourth inverter, and may receive the inverted input data or the test data and may latch and provide at an output node, the input data or the test data, upon the transition of the clock signal to a high state.

Abstract: System and methods for forming an integrated circuit using a standard cell library are provided. In some aspects, a method includes arranging cells from the standard cell library into a row between upper and lower power rails. Each cell includes a plurality of lateral nodes, at least one boundary region, and at least one dummy transistor. The method includes identifying a connection pattern of adjacent ones of the cells. The connection pattern is between (i) the lateral nodes of the adjacent cells and (ii) the upper and lower power rails. The method includes removing adjacent boundary regions of the adjacent cells based on the identified connection pattern of the adjacent cells, and modifying an arrangement of adjacent dummy transistors of the adjacent cells based on the removal of the adjacent boundary regions.