Patents by Inventor Ardeshir Namdar-Mehdiabadi
Ardeshir Namdar-Mehdiabadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9768790Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.Type: GrantFiled: May 10, 2016Date of Patent: September 19, 2017Assignee: Skyworks Solutions, Inc.Inventors: Ardeshir Namdar-Mehdiabadi, Darren Roger Frenette, John William Mitchell Rogers
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Patent number: 9531392Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.Type: GrantFiled: March 19, 2015Date of Patent: December 27, 2016Assignee: Skyworks Solutions, Inc.Inventors: Rachel Nakabugo Katumba, Darren Roger Frenette, Ardeshir Namdar-Mehdiabadi, John William Mitchell Rogers
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Publication number: 20160359494Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.Type: ApplicationFiled: May 10, 2016Publication date: December 8, 2016Inventors: Ardeshir Namdar-Mehdiabadi, Darren Roger Frenette, John William Mitchell Rogers
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Patent number: 9362925Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.Type: GrantFiled: May 21, 2015Date of Patent: June 7, 2016Assignee: Skyworks Solutions, Inc.Inventors: Ardeshir Namdar-Mehdiabadi, Darren Roger Frenette, John William Mitchell Rogers
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Publication number: 20160013797Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.Type: ApplicationFiled: March 19, 2015Publication date: January 14, 2016Inventors: Rachel Nakabugo KATUMBA, Darren Roger FRENETTE, Ardeshir NAMDAR-MEHDIABADI, John William Mitchell ROGERS
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Publication number: 20150349788Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.Type: ApplicationFiled: May 21, 2015Publication date: December 3, 2015Inventors: Ardeshir Namdar-Mehdiabadi, Darren Roger Frenette, John William Mitchell Rogers
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Patent number: 9065457Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.Type: GrantFiled: April 25, 2013Date of Patent: June 23, 2015Assignee: Skyworks Solutions, Inc.Inventors: Ardeshir Namdar-Mehdiabadi, Darren Roger Frenette, John William Mitchell Rogers
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Patent number: 8989332Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.Type: GrantFiled: February 26, 2014Date of Patent: March 24, 2015Assignee: Skyworks Solutions, Inc.Inventors: Rachel Nakabugo Katumba, Darren Roger Frenette, Ardeshir Namdar-Mehdiabadi, John William Mitchell Rogers
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Publication number: 20140177770Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.Type: ApplicationFiled: February 26, 2014Publication date: June 26, 2014Inventors: Rachel Nakabugo KATUMBA, Darren Roger FRENETTE, Ardeshir NAMDAR-MEHDIABADI, John William Mitchell ROGERS
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Publication number: 20130308735Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.Type: ApplicationFiled: April 25, 2013Publication date: November 21, 2013Inventors: Ardeshir Namdar-Mehdiabadi, Darren Roger Frenette, John William Mitchell Rogers
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Patent number: 8456206Abstract: Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.Type: GrantFiled: June 20, 2011Date of Patent: June 4, 2013Assignee: Skyworks Solutions, Inc.Inventors: Ardeshir Namdar-Mehdiabadi, Yong Hee Lee, Thomas Obkircher
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Publication number: 20120319747Abstract: Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Ardeshir Namdar-Mehdiabadi, Yong Hee Lee, Thomas Obkircher
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Patent number: 7215211Abstract: An (N?1)/N prescaler is provided, where N is an S power of 2. The prescaler uses only S flip-flops. The (N?1)/N prescaler receives a clock input from a high frequency oscillator, and provides an output line to a counter. The (N?1)/N prescaler receives a divide-by-(N?1) signal from the counter, and responsive to the divide signal, causes the prescaler to divide by a factor of (N?1); otherwise, the prescaler divides by a factor of N.Type: GrantFiled: June 10, 2005Date of Patent: May 8, 2007Assignee: Skyworks Solutions, Inc.Inventors: Tudor Lipan, Ardeshir Namdar-Mehdiabadi
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Publication number: 20060280280Abstract: An (N?1)/N prescaler is provided, where N is an S power of 2. The prescaler uses only S flip-flops. The (N?1)/N prescaler receives a clock input from a high frequency oscillator, and provides an output line to a counter. The (N?1)/N prescaler receives a divide-by-(N?1) signal from the counter, and responsive to the divide signal, causes the prescaler to divide by a factor of (N?1); otherwise, the prescaler divides by a factor of N.Type: ApplicationFiled: June 10, 2005Publication date: December 14, 2006Inventors: Tudor Lipan, Ardeshir Namdar-Mehdiabadi